Modeling next generation ARM cores to make computing even more smarter than it is today.

CPU Architecture and Performance Modelling.• Worked on different parts of branch predictor and I-cache pre-fetching in a cycle accurate C++ based simulator.• Evaluated performance improvement and impact on IPC for new developments in the core architecture.

• Worked in the domain developing digital logic simulator and encryption of RTL netlist for protection of intellectual property.• Developed a bunch to tools in C++ to encrypt RTL netlist which hide underlying gates and then simulate this encrypted netlist for correct functional output, power and delay. • The encrypted logic simulator produces exact same output, power and delay as produced by the un-encrypted netlist with minimal overhead.• Our research is aimed at reducing time to market for products which use IPs from other vendor, such as ARM® etc. and integrate it in their own design. • Our research can help IP vendor make their circuits public without revealing underlying circuit details. A client can then use it, simulate it and test the integration with their own design but won’t be able to replicate underlying structure of the circuit.• Once integration is verified, client can then go ahead with licensing for buying the IP.• We believe this greatly reduces time-to-market and avoids time consuming cycles of testing between IP vendor and the client.

• Mainly worked on floating point baseband processor implementation on Altera Stratix-4 FPGA for a potential 5G wireless technology. The processor performs computing FFTs, QAM demodulation, Clock recovery, frame synchronization, complex channel estimation and MMSE filtering.• Interfacing high speed-4 channel, 250MHz DACs and ADCs to FPGA using wishbone architecture. • The current technology works at 10 GHz and is based on Multiple Input-Multiple Output (MIMO) system. Our research is to reduce the hardware complexity of a digital wireless transceiver. Conventional MIMO system uses n-element (λ/2 spaced) array antenna with n-RF chains whereas our technology reduces the number of RF chains used for same number of orthogonal beams.• Currently working on next generation implementation of this technology which is planned to work at 28 GHz with a total baseband bandwidth of 1Gbps.

• Programming internal microcontroller of an RFIC using embedded C. The controller is used for RF front end control and faithful reception of wireless data working on 2G, 3G and 4G-LTE. It include writing algorithms for integration with baseband processor chip using high speed lvds connections and control singling. • Other job responsibilities include performance analysis of digital Rx chain, latency involved in filters, measurement of second-order intermodulation distortion (IM2) and the LO leakage Calibration of DCR MIMO-OFDM wireless RF transceiver chip using MATLAB and Xilinx FPGA.• Well acquainted with LNA (CMOS), HP/LP IIR and FIR filter, CIC decimation filter, duplexers, Quad band power amplifier (CMOS,SiGe,GaAs) with integrated TDD Tx-Rx switch for single SAW architecture, average power tracking using DCDC converters, RF SPnT switches, adaptive array antenna, DC notch and automatic repeat request for High Speed MIPI Interface standard DIG RF 4.0.

I was mainly involved in functional and system verification of VoIP phones.In particular, my responsibilities included verifying transport layer security (TLS) aspects of VoIP phones such as secure RTP, VPN, authentication mechanism and cryptographic abilities.To optimize the test suite I also worked on implementation of Virtual LAN and IEEE 802.1p based Quality of Service, AES, DES, Message Digest-5, SHA1/SHA256 and Diffie-hellman key exchange using Wind River Linux kernel. I also worked on system verification of WPA, WPA-2 and OFDM for mobile handsets based on IEEE 802.11a/b/g/n and VoIP mobile handsets on Aruba WLAN infrastructure.