Wayne Chen Email & Phone Number

Taiwan

Taipei City, Taiwan

• Lead Quality PM team to manage Consumer Notebook Envy, Pavilion, HP, Stream and Chromebook segment covering 35 NPI/Refresh platforms with 23M shipping volume each year• Consumer Notebook achieved Quality goal for 6 years in a row and contributed 10M USD warranty saving for FY20, 7.4M for FY21 and 8M for FY22• Team oversees End-to End product quality issue including hardware, software, firmware, manufacturing, supplier quality and customer experience concern from concept phase, development stage throughout mass production till end of product life cycle• Conduct regular Executive Level business review with R&D, Product Planning and Quality Management team • Initiated Quality/Reliability/Cost Saving program – Design for emerging country, USB port ESD advanced immunity, Plastic material audit plan, Hinge reliability enhancement, Sustaining product quality audit plan, COVID Rapid detection and mitigation war room and etc. to drive accelerated failure rate reduction and warranty saving• Two patents pendingo Determination of fan malfunction based on fan noise; Record ID 85898862, Patent Ref. 700239415WO01o Avoiding fan noise or slowdown caused by background tasks by comparing balance of 'in focus' activity; Record ID 85906224, Patent Ref. 700239744WO01

Taipei City, Taiwan

• Responsible for Consumer Notebook End-to-End product quality from early architecture phase to mass production and end of service life• Applied Design for X technique, NUD Risk Assessment, previous generation lesson-learn and social media data to improve the product quality throughout all development stages.• Applied data analyze skill on field quality index includes call data, social media review, service event and service part consumption to early detect product quality issue and release field resolution in timely manner• Managed customer product quality escalation from regional team to rapidly deploy field resolution to address customer issue. • Applied developed program manage skill to coordinate with R&D, Supply Chain, ODM and Customer facing team. • Achieved best seller of SPECTRE premium notebook in HP history and won HP President Award in 2016

Taipei, Taiwan

• Performed Design for Quality/Reliability assessment on notebook/tablet product in development phase• Performed failure analysis on field failure unit, identified root cause, provided corrective action and released 8D report• Performed FMEA on NUDD risk assessment • Drive field lesson learn prevention into design guideline, checklist and validation plan.• Established Taiwan Failure Analysis Laboratory of Notebook GBU• Co-published Notebook Extended Stress Testplan and owner for DFx Design Guideline • Evaluated waiver request based on reliability, field quality and customer experience impact• Audited ODM system validation test execution and reduced discrepancies• Audited factory safe launch report and identified quality risks• Delivered multiple projects for quality improvement, cost saving and warranty reduction

Taipei, Taiwan/Santa Clara, California, Us

*Architect lead of USB3.0 and iXVE(NVIDIA in-house PCIe endpoint)- Defined RTL micro-architecture, evaluated silicon performance and power consumption and resolved system level issues*Architect lead of MCP77/78(AMD platform single chipset) Low Power Feature bring-up - Led team for silicon bring-up and power optimization, worked across departments to resolve customer issues*Architect lead of HT3.0 LMM (Hypertransport Link Mode Management) - Defined micro-architecture, developed verification test plan, led team for silicon bring-up*Ran performance tuning for PCIe, SATA and MAC IP.*Handled the design issue between local design team and worldwide architect team*Developed system level and component level in-house low power schemes*Performed meaurement with lab instruments for silicon bring-up

Taipei City, Taiwan

*Implemented and developed RTL code of PCIe Gen1 MAC layer.*Maintained RTL code of PCIe Gen1 PHY PCS block and PHY hardmacro licensed from Rambus Semiconductor.*Defined micro-architectuce, participated the RTL design and verification of M1697(PCIe single chip for AMD platform), M5301(PCIe to AGP), M5291(PCIe to SATA) and M9211(PCIe TV tuner)*Performed system level RTL verification and silicon bring-up for M1695(PCIe tunnel chip for Hypertransport System) and M1697(PCIe chipset for AMD platform)*Applied Tektronics Logic Analyzer and CATC PCIe analyzer for silicon debugging

San Jose, California, United States

*Performed Hspice simulation to generate IBIS Models for IO buffer*Established in-house IBIS model generation flow and provided internal training to cross function team.*Resolved and answered customer technical issues.*Ran board level simulations with Cadence tool to verify IBIS models correlation with measurements.*Applied LAB instruments such as oscilloscope, spectrum analyzer and modulation analyzer for AC parameter measurements.

Master Of Science, Electrical Engineering

Bachelor Of Science, Mechanical Engineering