Staff Asic Product Engineer
● Collaborated with external foundry partners TSMC, UMC, SMIC process integration, product engineering and customer service team and internal product engineering, testing, planning and FA team on 12nm/16nm/28nm/ 40nm wireless communication and multimedia new product introduction (NPI) and mass production (MP) products and provided high level key projects status on major failure bins improvement action progress with yield and D0 forecast roadmap report to the top management. ● Managed NPI products with risk build authorization (RBA) ramp up tasks including tape out management, process window corner skew analysis, WAT devices analysis, test datalog analysis, yield correlation analysis, and coordinated internal and external cross team with all NPI issued resolved on time and lead the team to transfer to MP.● Managed to sustain MP yield and yield improvement actions with DOE, CIP, BKM, and defect reduction lot handling with wafer process, device and yield analysis and resulted yield improved 0.1%~3.0% on various products. ● Performed in-depth WAT devices, test datalog and yield analysis by utilizing Data Conductor and DataPower Exensio tools to investigate systematic low yield, single wafer low yield (SWLY), FACR/RMA root cause analysis and drive foundries to take immediate actions by identify excursion impact lot lists, inline process and tools correlation findings to minimize yield impact and improvement schedule.