Wayne, Chih Wei Chen
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Wayne, Chih Wei Chen Email & Phone Number

Staff ASIC Product Engineer at Synaptics
Location: Hsinchu County, Taiwan, Province of China 5 work roles 2 schools
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Role
Staff ASIC Product Engineer at Synaptics
Location
Hsinchu County, Taiwan, Province of China

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Wayne, Chih Wei Chen is listed as Staff ASIC Product Engineer at Synaptics based in Hsinchu County, Taiwan, Province of China. AeroLeads shows a matched LinkedIn profile for Wayne, Chih Wei Chen.

Wayne, Chih Wei Chen previously worked as Staff ASIC Product Engineer at Synaptics Incorporated and Senior Manager of Supply Chain Management and Service and Product Engineering at 訊崴技術有限公司 Xunweitech. Wayne, Chih Wei Chen holds Master Of Science - Ms, Electrical And Electronics Engineering from Michigan State University.

Profile bio

About Wayne, Chih Wei Chen

1. 16 years experience in advanced logic CMOS and Memory (speciality DRAM, low power DRAM, NAND flash, NOR flash, HBM) related products yield engineering analysis and supply chain management.2. Excellent experience in manage advanced logic CMOS foundries (TSMC, UMC, SMIC, PTC) and Memory Foundries and IC Design Houses (Samsung, SK Hynix, Micron, Toshiba/KIOXIA, PTC, SMIC, Nanya Technology, Winbond, ESMT, GigaDevice, AP Memory).3. Foundry process yield improvement experience: Advanced logic CMOS Products with technology node 130nm to 7nm and Memory Products with technology node from 90nm to 20nm.4. With experience foundry R&D NPI transferring to mass production, yield ramp up, process and product qualification and supply chain management and foundry production line audit.5. With experience in component level and wafer level ATE and SLT EFA/PFA analysis for yield improvement.

5 roles

Wayne, Chih Wei Chen work experience

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Staff Asic Product Engineer

Hsinchu County, Taiwan, Taiwan

● Collaborated with external foundry partners TSMC, UMC, SMIC process integration, product engineering and customer service team and internal product engineering, testing, planning and FA team on 12nm/16nm/28nm/ 40nm wireless communication and multimedia new product introduction (NPI) and mass production (MP) products and provided high level key projects status on major failure bins improvement action progress with yield and D0 forecast roadmap report to the top management. ● Managed NPI products with risk build authorization (RBA) ramp up tasks including tape out management, process window corner skew analysis, WAT devices analysis, test datalog analysis, yield correlation analysis, and coordinated internal and external cross team with all NPI issued resolved on time and lead the team to transfer to MP.● Managed to sustain MP yield and yield improvement actions with DOE, CIP, BKM, and defect reduction lot handling with wafer process, device and yield analysis and resulted yield improved 0.1%~3.0% on various products. ● Performed in-depth WAT devices, test datalog and yield analysis by utilizing Data Conductor and DataPower Exensio tools to investigate systematic low yield, single wafer low yield (SWLY), FACR/RMA root cause analysis and drive foundries to take immediate actions by identify excursion impact lot lists, inline process and tools correlation findings to minimize yield impact and improvement schedule.

Dec 2021 - Jun 2022

Senior Manager Of Supply Chain Management And Service And Product Engineering

Hsinchu County, Taiwan, Taiwan

● Managed DRAM, HBM, NAND, NOR, pSRAM memory product suppliers including Samsung, SK Hynix, Micron, KIOXIA, Micron, NTC, Winbond, ESMT, Giga Device, AP Memory, and supported TSMC 7nm/10nm products and CoWoS HBM process related tasks. Based on the principles of prevention, detection and disposition supplier management excellence and received Supply Chain Operation Team Award of the Year 2020 recognition.● Coordinated to RMA HBM IQC and slant cut issue dices successfully resulted saving 9.8 million USD potential loss, and received Star of HiSilicon Award, Hero Rescue Award ● Participated to setup internal KGD direct procurement system from indirect procurement system resulted saving X thousands USD per year procurement expenses and received Multi-Incentive Award recognition.● Published Known Good Die (KGD), High Bandwidth Memory (HBM), and Universal Flash Stored (UFS) supplier management guidelines including technology roadmap, products selection table, NPI corner skew guideline, MP yield criteria, inline and WAT SPC Cp/CpK review with R1/R2 rule, defect trend criteria, IQC/OQC benchmark criteria, FA analysis methodologies, reliability guidelines, and PCN classification criteria.● Hosted and managed suppliers QBR/QQR meetings with new products business plan, new product introduction discussion, quarterly yield, quality issue and scorecard review, and meeting minutes action items follow up.● Arranged suppliers monthly on-site meeting with NPI/MP yield update and yield forecast roadmap review, process inline/WAT trend chart with Cp/CpK R1/R2 rule review, top failure bins root cause finding with countermeasure update, defect trend chart review with CIP status, monthly reliability update, failure analysis status, and NPI/MP project status update.● Participated in supplier foundry audits for automotive and customer products with audit plan, result and ranking.

Dec 2017 - Apr 2021

Senior Product Engineer

Hsinchu City, Taiwan, Taiwan

● Managed Touch and Display Driver Integration (TDDI) & Display Driver IC (DDIC) products from NPI ramp to MP, and ensure the device characteristics, test datalog specification, and yield performance met the internal target.● Key role as foundry contact interface managed to co-work with TSMC, UMC and PTC on 40nm/55nm/80nm/ 90nm DOE, BKM, CIP and defect reduction yield improvement lot management and summarize the analysis result to internal team for process implementation decision making to achieve internal yield target. Tracking and handling systemic failure, low yield excursion and FACR/RMA wafer lots investigation, disposition and corrective actions follow up. ● Setup Datapower Exensio EDA system with new production information for CP yield and WAT data upload, and utilized for yield map, device and testing data log correlation check for yield analysis and improvement.

Sep 2015 - Nov 2017

Senior Product Engineering, Yield Enhancement, Quality Pcs Engineer

Taichung City, Taiwan

● Developed component level FT EFA analysis with with Advantest T5593 tester and DIMM system level tester to identity electrical failure mechanism and failure location for test spec analysis and test coverage optimization and FA analysis with countermeasure actions.● Developed wafer level CP EFA analysis with voltage/timing/temperature/shmoo dependency analysis and failure bit map (FBM) capability with HAMAMATSU PHEMOS-1000 and Micron Test Bench to identity failure location and co-worked with PFA team on SEM/TEM/EDX/OBRICH FA finding results to process integration engineers for process window optimization resulted yield improvement.● Published T5593 tester and DIMM system level test, and HAMAMATSU PHEMOS-1000 and Micron test bench SOP guidelines as newcomers hands-on experience training materials. ● Managed to lead 15 team members and collaborated with Singapore and USA supporting team for AMAT E3 Fault Detection & Classification (FDC) system setup and completed the system conversion within 6 months. ● Developed AMAT E3 FDC system training course and quizzes, and as a course instructor trained and certified more than 300 process and equipment engineers.

Dec 2007 - Sep 2015

Senior Nano Technology Integration Engineer

Hsinchu City, Taiwan, Taiwan

● Responsible for 0.13um customers lot handling, experiment lot planning and WAT and yield result analysis, and handled MPW shuttle tape out, process flow and WAT setup, device corner skew analysis, SPC and PCN review.● 4 times SWLY root cause finding champions in 2005.● Successful to transfer 55nm advanced technology from R&D to Fab including critical process release standard check, MPW tape out tasks, device corner target tuning window check and analysis, process flow and WAT setup, and DOE/CIP lots handling and analysis.

Jul 2004 - Jul 2007
2 education records

Wayne, Chih Wei Chen education

FAQ

Frequently asked questions about Wayne, Chih Wei Chen

Quick answers generated from the profile data available on this page.

What is Wayne, Chih Wei Chen's role at their current company?

Wayne, Chih Wei Chen is listed as Staff ASIC Product Engineer at Synaptics.

Where is Wayne, Chih Wei Chen based?

Wayne, Chih Wei Chen is based in Hsinchu County, Taiwan, Province of China.

What companies has Wayne, Chih Wei Chen worked for?

Wayne, Chih Wei Chen has worked for Synaptics Incorporated, 訊崴技術有限公司 Xunweitech, Micron Technology, and Tsmc.

How can I contact Wayne, Chih Wei Chen?

You can use AeroLeads to view verified contact signals for Wayne, Chih Wei Chen, including work email, phone, and LinkedIn data when available.

What schools did Wayne, Chih Wei Chen attend?

Wayne, Chih Wei Chen holds Master Of Science - Ms, Electrical And Electronics Engineering from Michigan State University.

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