Wayne Ellis

Wayne Ellis Email and Phone Number

Analog AI Custom Design
Wayne Ellis's Location
Greater Burlington Area, United States, United States
Wayne Ellis's Contact Details

Wayne Ellis personal email

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About Wayne Ellis

Memory IP Development Engineer * GF 22FDSOI ROM IP product development design lead * GF Sub-22nm Finfet ROM IP product development design leadFDSOI and FinFet circuit design technologist * Drive technology PVT analysis for design point selection * Define limits for functionality to support Low Voltage product operation * Provide engineering insights for product design to meet Burn In requirements * SRAM circuit designUtilize industry experience and expertise to drive patent strategy, valuation, assertion * Claims development * Indentify valuable patents, determine infringing products, develop claim charts * Analyze patents and technologies for internal development or acquisition30 yrs industry experience in DRAM, eDRAM and eSRAM product design and development. * 30+ Patents granted in fields of VLSI product and technology. * Member of Patent Review boards Rambus, IBM, Qimonda, Innovative Silicon. * 30+ papers on DRAM circuit and technology published in refereed journals. * Adjunct professor; University of Vermont Continuing Education 2000 - 2005. * Ericsson - Linkoping Distinguished visiting professor, Univerity of Linkoping Sweden, 2002.

Wayne Ellis's Current Company Details

Analog AI Custom Design
Wayne Ellis Work Experience Details
  • Asicnorth
    Senior Design Engineer
    Asicnorth May 2021 - Dec 2023
    * Retired Dec 2023* Analog AI Custom circuit design/ analysis/ layout* Advanced test site bit array integration
  • University Of Vermont
    Adjunct Professor
    University Of Vermont Jan 2019 - Jan 2020
    Burlington, Vermont, Us
    E261 Semiconductor Materials/ Devices - Utilize DRAM, SRAM, ROM bitcells to develop PSpice models/ analysis - Utilize PSpice analysis to explore effect of process defect/ reliability mechanisms on circuit functionality. - Develop Yield Modelling analysis to explore effects of lithography options and Defect Density - Develop Custom VLSI Circuit design techniques for RAM sense amplifiers
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  • Invecas
    Memory Ip Development
    Invecas Aug 2016 - Jun 2019
    Santa Clara, California, Us
    ROM IP design Lead*** retiring June 30, 2019* GF 22FDSOI ROM products - Cost Performance family (2K - 1.1Mb) - ULP Family (2K - 1.1Mb)* GF Sub-22nm FinFet ROM Products - Co - Development with west coast team (Develop experienced SRAM designers as ROM designers) - Lead parallel development of Cost Performance and High Density Cost Performance product families
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  • Snowflake Ridge Consulting Llc
    Manager
    Snowflake Ridge Consulting Llc Jan 2016 - Aug 2016
    Simulation/ characterization of FDSOI and FinFet technologiesTechnology PVT functionality researchExtraction - schematic correlationSRAM Circuit design
  • Rambus
    Ip Strategy Director
    Rambus Feb 2014 - Dec 2015
    San Jose, Ca, Us
    Drive intellectual property development strategy in key areas relating to Rambus business;* Products* Technologies * Standards Provide expertise for cross functional teams including IPD, R&D and Business Development to analyze patents and technologies for internal development or acquisition.Technical Conference volunteer: * International Integrated Reliablity Work Shop (IIRW) Management and Technical Program committees (2015, 2014, 2013)
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  • Rambus
    Senior Principal Engineer
    Rambus Feb 2010 - Feb 2014
    San Jose, Ca, Us
    * Patent Engineer working with Rambus IPD* Mobile memory product architecture, circuit design, simulation* DDRx architecture research* Rambus Patent committee (memory area specialty)* Develop IP for future memory products* In depth DRAM array design/ test insightsConferences:* International Integrated Reliablity Work Shop (IIRW2013) management committee - Discussion Group Chair - Technical Review Committee memberRecent Publications: * University of Vermont invited graduate seminar (March 2013) - "Server memory system operation and DRAM Design" * University of Santa Clara (CA) invited graduate seminar (Jan 2013) - " Server Benchmarks and memory utilization" * International Integrated Reliabillity Workshop (IIRW2012) - "DRAM Operating States and Burn In", W. Ellis, G. Yip, J. Hong, 2012 IEEE IIRW Final Report, pp144-146,
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  • Innovative Silicon Inc.
    Director Of Technical Marketing
    Innovative Silicon Inc. Feb 2008 - Sep 2010
    Santa Clara, Ca, Us
    Work with company research and development to define product requirements. Explore and develop new product opportunities. - Demonstrated in April 2008 that the then current 2D structures suffered Hot Carrier induced operating life degradation. - This initiaited new research into new structures to improve reliability. - Provided technical review to insure quality of customer presentations.
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  • Qimonda North America
    Principal Cellularram Concept Engineer
    Qimonda North America Apr 2006 - Feb 2008
    Munich, ., De
    Work with customers to align Qimonda CellularRAM product line road map with base band processor road map requirements. Co-Chair of CellularRAM Working Group; develop roadmap of functional standards evolution for CellularRAM operation aligned with base band processor needs. Member JEDEC PSRAM2 Standard working group. Technical advisor to Qimonda Product Design, Test and Product Sales teams.
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  • Ibm
    Senior Scientist
    Ibm Jun 1975 - Apr 2006
    Armonk, New York, Ny, Us
    Team Leader/ manager DRAM product development (4Kb - 512 Mb), DRAM technology interface, Team leader 65 nm compilable eSRAM design development. DRAM Patent review board Chairman
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  • Irvine Sensors
    Manager Product Development
    Irvine Sensors 1994 - 1996
    * 320 Mb Stacked DRAM product design team manager.* Stacked DRAM module test development.* Stacked DRAM module Burn In development.

Wayne Ellis Skills

Semiconductors Circuit Design Vlsi Ic Asic Verilog Simulations Dram Eda Analog Soc Semiconductor Industry Characterization Research Electronics Very Large Scale Integration Graduate Education Mixed Signal Integrated Circuits Higher Education Application Specific Integrated Circuits

Wayne Ellis Education Details

  • University Of Vermont
    University Of Vermont
    Materials Science
  • University Of Vermont
    University Of Vermont
    Materials Science

Frequently Asked Questions about Wayne Ellis

What is Wayne Ellis's role at the current company?

Wayne Ellis's current role is Analog AI Custom Design.

What is Wayne Ellis's email address?

Wayne Ellis's email address is wa****@****rth.com

What is Wayne Ellis's direct phone number?

Wayne Ellis's direct phone number is +180285*****

What schools did Wayne Ellis attend?

Wayne Ellis attended University Of Vermont, University Of Vermont.

What are some of Wayne Ellis's interests?

Wayne Ellis has interest in Flyfishing, Rock A Billy, Guitar Building/ Playing, Tennis, Golf, Professional, Tele Skiing.

What skills is Wayne Ellis known for?

Wayne Ellis has skills like Semiconductors, Circuit Design, Vlsi, Ic, Asic, Verilog, Simulations, Dram, Eda, Analog, Soc, Semiconductor Industry.

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