Organisation Bring-up and Expansion, Resource Development & Management, Risk Management, Project Management, Design Verification.

Front-end Technical Leader of the company, TFM, Resource Management, Risk Management, Project Management, Design Verification, Verification Architecture, Formal Property Verification, IP-level Verification, CPU Sub-systems, SoC Verification.

- Design Verification Leader of the HPC Department.- Delivered fully-verified ARM's Cortex A-profile and M-profile CPU sub-systems and in-house IPs.- TFM

- Design Verification Leader of the HPC Department.- Delivered fully-verified ARM's Cortex A-profile and M-profile CPU sub-systems and in-house IPs.- TFM

- DV Lead in the department of Computing and Artificial Intelligence, verifying ARM-based CPU subsystems spanning across most of the state-of-the-art Cortex A-profile CPUs.- Experienced in AMBA interfaces and ARM ecosystem.- Program Manager on DV's Tools, Flows and Methodologies (TFM).- Experienced in pre-silicon Design Verification from RTL to Netlists.- Experienced in post-silicon patterns generation, analysis, debugging and flow automation.- Brought up a DV team specialising in the verification of ARM CPU sub-systems.

- Verification Architect.- Chaired technical paper reviewing panel of Intel's DTTC Technical Conferences.- Experienced in most of the I/O interfaces and controllers of Intel Chipsets (PCH, MCH, ICH).- Definition and development of VIPs.- Scoreboard framework creator.- Experienced in Intel Chipset's full-chip verification.

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