Wee Khang Chong Email & Phone Number

Penang, Malaysia

GF 12nm HPSC project (Oct 2023 - Present)• Co – leads the HSIO subsystem implementation taskforce group of 6 members, mainly to perform DFT, STA and radiation hardened cell implementations.• Runs weekly meetings to oversee task progress and resolve design issues• Develops design automation scripts to speed up and standardize block radiation hardening activities.• Work closely with layout team in performing blocks to meet timing, gate efficiency and good area utilization… Show more GF 12nm HPSC project (Oct 2023 - Present)• Co – leads the HSIO subsystem implementation taskforce group of 6 members, mainly to perform DFT, STA and radiation hardened cell implementations.• Runs weekly meetings to oversee task progress and resolve design issues• Develops design automation scripts to speed up and standardize block radiation hardening activities.• Work closely with layout team in performing blocks to meet timing, gate efficiency and good area utilization percentage.GF 12nm Mock Chip tapeout (Jan 2023 – Sept 2023)• Perform power – gated block physical implementation from synthesis to GDSII.• Main supporter in enabling new features, such as new in – house DFT methodology, Tessent memoryBIST and radiation hardened cells implementation.• Pioneers footer isolation cell implementation. The works include power intent format migration from CPF to UPF, power domain isolation assessment and synthesis/layout flow script enhancement.• Perform layout place & route activities such as floor planning, Power Mesh Built, Placement Optimization, Clock Tree Synthesis, Routing and DFM Optimization.• Perform postlayout verification such as DRC, LVS, Conformal Low Power LEC and Power Analysis (IR Drop, PGEM, SHE).TSMC 16nm PCIe Gen5 SSD controller tapeout (Aug 2020 – Feb 2023)• Full chip owner for synthesis and STA timing closure. • Key contributor in developing automation scripts to perform custom timing ECOs due to EDA tool restriction• Analyze and perform inter – blocks clock skewing. Plays roles as coordinator for interface timing fixing in between subblocks owners• Perform scan reordering and logic path rebuilding to relax scan path timing and increase scan clocks frequency within full chip. Technically challenging due to changes on scan configuration in the final phase of project and respin restrictions. Show less

Penang, Malaysia

TSMC 16nm NVMe PCIe Gen 4 SSD controller tapeout (2 Revs, Sept 2018 – Jun 2020)• In charge of block and subsystem gatelist synthesis, with DFT implementation that includes General Scan feature, scan stitching, I/O wrapping, XOR tree scan compression and ram BIST insertion to achieve good ATPG coverage.• Perform MMMC STA timing and reliability analysis. • Develop and maintain SDC timing constraints to address the real timing violations. • Drive design to timing closure with ECO… Show more TSMC 16nm NVMe PCIe Gen 4 SSD controller tapeout (2 Revs, Sept 2018 – Jun 2020)• In charge of block and subsystem gatelist synthesis, with DFT implementation that includes General Scan feature, scan stitching, I/O wrapping, XOR tree scan compression and ram BIST insertion to achieve good ATPG coverage.• Perform MMMC STA timing and reliability analysis. • Develop and maintain SDC timing constraints to address the real timing violations. • Drive design to timing closure with ECO scripts and to meet other signoff requirements such as max capacitance, max transition, glitch/noise and clock skew checks. Show less

Muar, Johore, Malaysia

Dedicated to training under Central Engineering Department. Tasked to data analysis and parameter optimization in wafer pre-assembly process.

Master Of Science - Ms, Electronic System Design Engineering

Bachelor’S Degree, Electrical And Electronics Engineering