Designed and implemented FPGA in iBypass 40Gb intelligent bypass switch. FPGA architecture and design from concepts. Industry's first 40G intelligent 40G bypass switch using FPGA to realize bypass/tap functions and other functions including micro-second heartbeat packets generation/detection, micro-burst detection and bandwidth utilization calculation. works included FPGA design specification, RTL coding, simulation, place and route, timing closure. Altera Stratix V 5SGXMA5H2 FPGA. Altera 40G Ethernet MAC/PHY IP and DDR3 controller IP were used.

Designed FPGA (Altera Arria GX) for iBypass-HD 32 1G ethernet ports bypass switch's daughter card Designed FPGA (Altera Stratix III) for iBypass-HD 32 1G ethernet ports bypass switch mother board, the main function of mother board FPGA is interfacing with CPU card through PCI bus, programing the daughter cards FPGA, interfacing with daughter cards FPGA with parallel control bus.Maintained and enhanced the legacy products FPGAs (Both Xilinx and Altera).

MLPPP packet processor FPGA in U4EA’s Fusion500 Quad T1/E1card without third party IP. The design was implemented in Altera's Cyclone III EP3C40 using Verilog HDL.WLAN controller hardware for cost reduction and function Improvement. The design included PowerQUICC II Pro MPC8343E, DDR SDRAM,10/100/1000 Ethernet, and CPLD. Designed FPGA for ATM to Ethernet Bridge using Verilog HDL and Altera's Cyclone III EP3C25. The design converted ATM cells to Ethernet packets and Ethernet packets to ATM cells.

Loea Corp’s next generation 71GHz-86GHz E-band Multi-gigabit data rate radio Base Band Processor FPGAThe Base Band Processor FPGA gets fiber diff signal data from fiber optic transceiver, Inserts framing and service channel, passes it to QPSK modem’s I and Q inputs in fiber to radio transmit path. In radio to fiber receive path, the Base Band Processor gets the I and Q signal from QPSK modem, corrects the I and Q signals possible phase ambiguity issue, extracts the service channel data and routes it to Ethernet switch. The implementation is done using Verilog HDL and Altera's Stratix GX FPGA

Designed and implemented Verilink's Ethernet over SDH multi-service access platform hardware including Viewlogic schematic capture and FPGA/CPLD design. The EOS Multi-service platform includes up to 16 10/100 Ethernet ports, 1 Gigabit Ethernet port, 4 E1 ports, 1 E3 port, and a STM-1uplink. Designed and implemented Verilink's next generation IAD hardware including Viewlogic schematic capture and CPLD design. Designed and implemented Larscom’s Ethernet over SONET (EoS) multi-service access Platform hardware including high speed PCB design, hot-swappable DC-DC power supply board design, CPLDs and FPGA design.Designed a FPGA to replace an obsolete 16-bit microcontroller. The 16-bit microcontroller (PAC1000) was mainly used to do the time slot allocation of DS0s among DTE1, DTE2 and AUX ports depending on the different mapping configurations.