Proficient in SoC front end validation flow- 8 years of experience in front end validation. (2015 - now)- Drive Technical Readiness taskforce to evaluate technical challenges and do early preparation before execution starts.- Analyze design specification and RTL codes, develop focus or synthetic tests to validate respective design feature.- Mainly focus on interconnectivity and IP parameter configuration validation. Ensure interoperability between IPs are validated and compatible at SoC level.- Develop and conduct test plan review, simulation waveform review with Architects and respective stakeholders.- Experience to debug under different environments such as simulation, emulation, FPGA and post silicon environment.- Continuous improvement in testplan by doing postmortem analysis on escape bug or coverage gap- Experience in building testbench and integrate verif component such as BFM(bus behavioural model) into the testbench- Good understanding in UVM or OVM methodology.- Proficient in system verilog language for test coding.- Good experience in developing perl scripts for innovation and automation task.Proficient in PCIe protocol- 5 Years of experience in DMI/RLINK/PCIe validation (2018 - now)- Good understanding on how PCIe is configured or enumerated by software at system level.- At low level, also processed skillful knowledge on PCIe link training happens and how transactions are transmited through PCIe link. Packet level knowledge such as TLP, DLLP, Ordered Sets are also mastered.- Familiar with all PCIe low power states such as L0s, L1, and L23.Experience in RTL integration flow- Worked on integrating IP(RTL component and Verif component) into SoC model.- Bring up basic test to ensure the integrated RTL and verif component are functional before passing the model to validator for mass validation.- Experience in integrating HSIO IPs such as PCIe, DMI, and RLINK.

Drive test strategy develop testplan:- Responsible to create test plan in commercial OS environment such as Windows, Android, and Linux to validate hardware (IP block or CPU feature)- Work with Designer, Firmware/Bios developer from different geographical regions to enable test content.- Analyze test failure, debug and narrow down the issue. Work with respective designer and Architects to root cause it - Area of expertise is hardware power management such as CPU c states, p states, s states and device low power states.