Weikai Sun Email & Phone Number

- Helping engineering teams to scale up to enable hyper-growth- Bringing semiconductor and system design process to AI era- Stay tunned ...

Sunnyvale, California, Us

Drive analog design platform strategy, roadmap, and key differentiated technology developmentwww.synopsys.com/custom

San Jose, California, Us

Inphi was acquired by Marvell (NASDAQ: MRVL) in a 10B$ deal In April'2021https://finance.yahoo.com/news/marvell-snap-inphi-10b-chip-101314556.html

San Jose, California, Us

San Jose, California, Us

- Establish and manage Inphi CAD & Implementation organization, with functional groups including CAD, custom layout, digital P&R, DFT, and ESD- With CAD & Implementation as central engineering resource, effectively and efficiently support all Inphi product development, with process technologies ranging from 130nm to finfet, from CMOS to III-V- Build up and improve Inphi design methodologies, including digital sim/DV, AMS, SP&R, analog circuit sim, custom layout, and physical/electrical verification- Focus on scalability and team growth, including establish chip leads on CAD, custom layout, and physical design- Hands-on project execution throughout product development life cycles, with cooperation cross functional groups- Integrate Cortina System acquisition in Sept’14, biggest acquisition for Inphi- Strategically plan and manage resources, ranging from contractors, design services, EDA & IP vendor relationship and contract negotiations, and HW resources (servers, storages, switches, filers). Significantly contribute to company bottom line while enabling Inphi product development

Sunnyvale, California, Us

- Streamlining CAD operation/support from initial program resource planning, project support, technology interfacing, and IP/test chip delivery. Managed and grew World-Wide CAD team to 50+ engineers- Managing CAD and Layout team supporting Embedded Memory, Logic Library, and various Mixed-signal Interface and Analog IP design teams, consisted of 20+ product lines and 800+ designers globally. IPs are designed and released to 10+ foundries and process technologies- Merging multiple design flows from multiple IP acquisitions (Virage/MIPS) into single Unified Design Flow (UDE), reducing overhead and improving productivity up to 50%. Major impacted area including data management system, foundry data management, bug tracking system, and various part of front-to-back end AMS design flow- Streamlining Layout operation from custom quote, process and back end evaluation, to scheduling and executing 20+ programs concurrently- Successfully grew layout team to 80+ engineers worldwide. Established central layout design methodology to ramp up new hires up to speed of complex memory physical design flow and maintain consistent process and quality of multi-site development

Santa Clara, Ca, Us

- Built up and manage CAD team (5 engineers) to build flow/methodology and infrastructure for complete SoC design flow- Define and implement Tabula AMS design environment infrastructure, including both custom and semicustom (SP&R) design and construction flow, standard cell library build/char/QA/release, physical design flow for fabric tile assembly using Cadence Space based Router (CSR), electrical and physical verification methodology and flow, sign off analysis and verification, database management across groups, and tape out procedure and checklist- In charge of vendor relation, including existing and new tool budget, business negotiation and transaction, and IP transaction- Engage with foundry as external foundry manager role, including design collaterals, design team and foundry communications, foundry roadmap discussion, and tapeout interface and activities- Successful tapeout of 40nm process high performance high complexity FPGA

Us

- Built up and manage a group of CAD engineers (12 engineers across US and India) to develop custom design flows/methodologies and provide support for design teams- Develop, maintain, and enhance robust Montalvo custom and semi-custom design methodology and environment that support 100+ IC design and implementation engineers developing high performance high complexity x86 microprocessor- Successful test chip tapeout using 65nm HP CMOS process- Develop and maintain Parasitic extraction methodology, physical verification environment (DRC/LVS/ANT/EM/DFM), Power and Power-grid integrity analysis flow, custom circuit and layout static checks, chip integration methodology, and low-power semi-custom flows- Close interaction with design teams to identify design issues, setup proper goals and approaches to address the issues - Identify, evaluate, and incorporate new CAD tools into existing design flow to increase design quality and productivity

Fremont, Ca, Us

- Built up and manage a small group of CAD engineers (3 engineers across US and Singapore) to provide support for design teams- Develop, maintain, and enhance robust Volterra mixed-signal design methodology and environment that support 20+ IC design engineers- Develop and maintain Schematic Driven Layout environment based on PCELL to boost physical design productivity- Develop and maintain Process Development Kit (PDK) for all Volterra proprietary leading edge high voltage process technologies- Built tapeout infrastructure and sign off checks, resulting in much reduced chip design cycle time, and 50% reduction in number of chip re-spin- Volterra went IPO July 2004

- Built up and manage a group of S/W engineers (4 direct reports, 12 matrix reports)- Technical and product marketing for extraction (cell based and device level, hierarchical and flat), process variation, inductance, timing, signal integrity, and power solutions- Define, develop, and manage the next generation tools on signal integrity, power (net) analysis, and power optimizations- Strategic customer relation and support- Achieved annual revenue of $10M+ from products under my group, with customers ranging from leading ASIC and Semiconductor component vendors- Cadence eventually bought Celestry in 2002 for $100M+

Berkeley, California, Us

- Built up and managed parasitic extraction group (5 engineers), performed technicalmarketing duties for parasitic extraction tools- Built infrastructures for QA testing suites and release process- Hands-on pre-sales benchmarking and evaluation process for key accounts- Responsible for the interface definition with LEF/DEF and GDSII, and fitting our tools in Cadence and Avanti backend physical design flows- Provided rules for core geometry decomposition technology- Developed and implemented modeling and geometry partitioning modulesfor Nautilus extraction tool- Technical contact for SEMATECH project “Chip Parasitic Extraction and Signal Integrity Verification.

Ph.D, Computer Engineering

M.S., Radio Engineering

Education record