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o 20 years’ experience of building up flows/methodologies/infrastructures and delivering physical implementation for analog/mixed-signal chips, SoC, microprocessors, and broad spectrum of semiconductor IPs, using various process technologies (from 0.35um HV to 14nm finfet). Built design flow include high level behavioral modeling, front end synthesis and optimization, schematic to layout automation, custom circuit front to back flow, chip level back end extraction and analysis, DFM, semi-custom design flows, and tapeout infrastructure. Built in house Standard Cell libraries, including characterization methodology, various electrical and physical views.o 5+ years of design, development, and marketing of large-scale software applications/systems, including 3D full chip parasitic extraction, 3D field solver, power and signal integrity solutions. Full project life cycle experience includes product positioning, technical marketing, planning and scheduling, integrating, testing, release, and customer supporto Ultima Interconnect Technology (later acquired by Cadence): created 3D extraction and SI/power tools, achieved $10M annual revenue runrateo Volterra Semiconductor: created complete AMS CAD flow, advanced HV process technologies and related PDK. The new flow and process resulted in 50% reduction in number of chip respin. Two years after I jpined, Volterra went Public on Nasdaqo Montalvo Systems: methodology for x86 microprocessors, including custom circuit front to back flow, block and chip level back end sign-off analysis, DFM, and semi-custom SP&R flows. Montalvo designed the 1st Industry asymmetric core uProcessor architectureo Tabula: complete design flow to deliver high end FPGA. Successful 40nm tapeout, and 22nm development (industry's 1st finfet process)o Synopsys: scale up CAD team with 50+ engineers, support 800+ globally distributed AMS designers across variety of hard IPo Inphi: establish central engineering CAD & Implementation organization, with functional groups including CAD, custom layout, digital P&R, DFT, and ESD. In 7 years, lead and help grow Inphi 10x in revenue ($80M to ~ $800M) and head count (100 to ~ 1000) . Inphi was acquired by Marvell April'2021 for $10B.o Synopsys: leading Synopsys analog and mixed-signal IC and system design platform CustomCompilero Published over 12 techniques papers, including 2 in IEEE Transactions.
Sun Consulting
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FounderSun Consulting Dec 2024 - Present- Helping engineering teams to scale up to enable hyper-growth- Bringing semiconductor and system design process to AI era- Stay tunned ...
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Vp Of EngineeringSynopsys Inc Mar 2021 - Dec 2024Sunnyvale, California, UsDrive analog design platform strategy, roadmap, and key differentiated technology developmentwww.synopsys.com/custom -
Vp, EngineeringInphi Corporation Apr 2020 - Mar 2021San Jose, California, UsInphi was acquired by Marvell (NASDAQ: MRVL) in a 10B$ deal In April'2021https://finance.yahoo.com/news/marvell-snap-inphi-10b-chip-101314556.html -
Associate Vp, EngineeringInphi Corporation Apr 2018 - Apr 2020San Jose, California, Us
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Sr. Director, Cad And ImplementationInphi Corporation Apr 2014 - Apr 2018San Jose, California, Us- Establish and manage Inphi CAD & Implementation organization, with functional groups including CAD, custom layout, digital P&R, DFT, and ESD- With CAD & Implementation as central engineering resource, effectively and efficiently support all Inphi product development, with process technologies ranging from 130nm to finfet, from CMOS to III-V- Build up and improve Inphi design methodologies, including digital sim/DV, AMS, SP&R, analog circuit sim, custom layout, and physical/electrical verification- Focus on scalability and team growth, including establish chip leads on CAD, custom layout, and physical design- Hands-on project execution throughout product development life cycles, with cooperation cross functional groups- Integrate Cortina System acquisition in Sept’14, biggest acquisition for Inphi- Strategically plan and manage resources, ranging from contractors, design services, EDA & IP vendor relationship and contract negotiations, and HW resources (servers, storages, switches, filers). Significantly contribute to company bottom line while enabling Inphi product development
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Sr Manager, Cad/LayoutSynopsys Aug 2011 - Mar 2014Sunnyvale, California, Us- Streamlining CAD operation/support from initial program resource planning, project support, technology interfacing, and IP/test chip delivery. Managed and grew World-Wide CAD team to 50+ engineers- Managing CAD and Layout team supporting Embedded Memory, Logic Library, and various Mixed-signal Interface and Analog IP design teams, consisted of 20+ product lines and 800+ designers globally. IPs are designed and released to 10+ foundries and process technologies- Merging multiple design flows from multiple IP acquisitions (Virage/MIPS) into single Unified Design Flow (UDE), reducing overhead and improving productivity up to 50%. Major impacted area including data management system, foundry data management, bug tracking system, and various part of front-to-back end AMS design flow- Streamlining Layout operation from custom quote, process and back end evaluation, to scheduling and executing 20+ programs concurrently- Successfully grew layout team to 80+ engineers worldwide. Established central layout design methodology to ramp up new hires up to speed of complex memory physical design flow and maintain consistent process and quality of multi-site development
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Director, CadTabula Apr 2008 - Aug 2011Santa Clara, Ca, Us- Built up and manage CAD team (5 engineers) to build flow/methodology and infrastructure for complete SoC design flow- Define and implement Tabula AMS design environment infrastructure, including both custom and semicustom (SP&R) design and construction flow, standard cell library build/char/QA/release, physical design flow for fabric tile assembly using Cadence Space based Router (CSR), electrical and physical verification methodology and flow, sign off analysis and verification, database management across groups, and tape out procedure and checklist- In charge of vendor relation, including existing and new tool budget, business negotiation and transaction, and IP transaction- Engage with foundry as external foundry manager role, including design collaterals, design team and foundry communications, foundry roadmap discussion, and tapeout interface and activities- Successful tapeout of 40nm process high performance high complexity FPGA -
Custom Cad ManagerMontalvo Systems Nov 2005 - Apr 2008Us- Built up and manage a group of CAD engineers (12 engineers across US and India) to develop custom design flows/methodologies and provide support for design teams- Develop, maintain, and enhance robust Montalvo custom and semi-custom design methodology and environment that support 100+ IC design and implementation engineers developing high performance high complexity x86 microprocessor- Successful test chip tapeout using 65nm HP CMOS process- Develop and maintain Parasitic extraction methodology, physical verification environment (DRC/LVS/ANT/EM/DFM), Power and Power-grid integrity analysis flow, custom circuit and layout static checks, chip integration methodology, and low-power semi-custom flows- Close interaction with design teams to identify design issues, setup proper goals and approaches to address the issues - Identify, evaluate, and incorporate new CAD tools into existing design flow to increase design quality and productivity -
Cad ManagerVolterra Semiconductor Nov 2001 - Nov 2005Fremont, Ca, Us- Built up and manage a small group of CAD engineers (3 engineers across US and Singapore) to provide support for design teams- Develop, maintain, and enhance robust Volterra mixed-signal design methodology and environment that support 20+ IC design engineers- Develop and maintain Schematic Driven Layout environment based on PCELL to boost physical design productivity- Develop and maintain Process Development Kit (PDK) for all Volterra proprietary leading edge high voltage process technologies- Built tapeout infrastructure and sign off checks, resulting in much reduced chip design cycle time, and 50% reduction in number of chip re-spin- Volterra went IPO July 2004 -
Director Physical AnalysisUltima/Celestry Jan 2001 - Nov 2001- Built up and manage a group of S/W engineers (4 direct reports, 12 matrix reports)- Technical and product marketing for extraction (cell based and device level, hierarchical and flat), process variation, inductance, timing, signal integrity, and power solutions- Define, develop, and manage the next generation tools on signal integrity, power (net) analysis, and power optimizations- Strategic customer relation and support- Achieved annual revenue of $10M+ from products under my group, with customers ranging from leading ASIC and Semiconductor component vendors- Cadence eventually bought Celestry in 2002 for $100M+
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ManagerUltima Jan 1996 - Dec 2000Berkeley, California, Us- Built up and managed parasitic extraction group (5 engineers), performed technicalmarketing duties for parasitic extraction tools- Built infrastructures for QA testing suites and release process- Hands-on pre-sales benchmarking and evaluation process for key accounts- Responsible for the interface definition with LEF/DEF and GDSII, and fitting our tools in Cadence and Avanti backend physical design flows- Provided rules for core geometry decomposition technology- Developed and implemented modeling and geometry partitioning modulesfor Nautilus extraction tool- Technical contact for SEMATECH project “Chip Parasitic Extraction and Signal Integrity Verification.
Weikai Sun Skills
Weikai Sun Education Details
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University Of California, Santa CruzComputer Engineering -
Southeast UniversityRadio Engineering
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No.10 High School
Frequently Asked Questions about Weikai Sun
What company does Weikai Sun work for?
Weikai Sun works for Sun Consulting
What is Weikai Sun's role at the current company?
Weikai Sun's current role is Technical, Strategic, and Innovative Executive -- getting things done by bringing together, motivating, coordinating, and setting goals for talented teams.
What is Weikai Sun's email address?
Weikai Sun's email address is ws****@****phi.com
What is Weikai Sun's direct phone number?
Weikai Sun's direct phone number is +140885*****
What schools did Weikai Sun attend?
Weikai Sun attended University Of California, Santa Cruz, Southeast University, No.10 High School.
What skills is Weikai Sun known for?
Weikai Sun has skills like Asic, Soc, Eda, Semiconductors, Ic, Verilog, Mixed Signal, Vlsi, Leadership, Semiconductor Industry, Integrated Circuit Design, Communication.
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