Manage the R&D department of Goodix Audio Business Unit which included analog mixed-signal IC design and verification, digital IC design and verification, silicon validation, layout, physical design, software algorithm and project management teams in Dallas, Shanghai, Shenzhen and Bangalore.Build the R&D organization to innovate and develop audio amplifier portfolio that focus on performance, efficiency, system cost, and reliability for the consumer and automotive market segments from ground up.

Led >15 analog mixed-signal resources from various geographic locations on IC development from project kickoff to volume production ramping which includes design, implementation, direction, resource, schedule and chip level integration for high-volume ambient light sensors for mobile device application.Interfaced and communicate with high-volume key customer on weekly basis on progress, milestones and design reviews.Translate system level specifications to architecture and circuits blocks specifications for implementation.Drive, share and leverage design, methodology, architecture and technology transfer within and across business units.Innovation resulted in 2 patent applications.

Drive the Design Enablement for 22FDX (22nm FDSOI process technology) in the area of Analog and Mixed-Signal Circuits for RF ICs design.Data conversion design including high speed energy efficient ADC for scalable 5G radio application.Power Management design including high-PSRR LDOs, nanoseconds, fast settling LDOs, back-gate bias sub-system, positive and negative high-voltage switched-capacitor charge-pumps.Baseband analog mixed-signal circuits design including low power trans-impedance amplifier for WiFi 802.11ac.Customer engagement, field application and IP vendor/partner training and workshop.Created Analog Design and Layout Best Practice and Guidelines workshop presentation materials for 22FDX customer.Innovation resulted in 3 US patents and 1 disclosure.

Led power management sub-system for multi-standard mobile cellular transceiver SoC products in 40nm and 28nm.Increased and extended responsible to include various analog and mixed-signal baseband circuits design for signal chain, calibration and correction sub-systems.Responsible for Nvidia’s 1st generation of baseband circuits design for current mode receiver to meet cellular standards (2G, 3G, 4G LTE).Co-created analog, mixed-signal layout guidelines and training in 28nm for the organization.

Analog and mixed-signal circuits and systems design for medical imaging system.Responsible for the architecture and circuit design of ultra-low power 12-bit 40Msps ADC using novel hybrid architecture for ultra-low power, high-channel count, ultrasound receive AFE IC.Developed ultrasound digital receive front-end which includes digital beam forming algorithm (both interpolation and phased rotation method to support system with linear array and phased array transducers), mid-end digital signal procesing including B-Mode for tissue and organ imaging and F-Mode (color and power Dopler) for blood flow imaging and back-end image enhancement in Matlab for FPGA prototype implementation.Developed ultrasound receive analog-front-end circuit (LNA, TGC, PGA, AAF, ADC) models including their associated non-idealities in Matlab for use in system development.Help build IC design team, infrastructure, flow and methodology in the R&D organization.Co-authored proposal and awarded multi year R&D project funding in the area of bio-potential sensing and magnetic resonance imaging.

Developed 3 generations of multi-standard digital+analog TV/STB/SAT tuners in RFCMOS 130nm process.Hands-on design of analog baseband circuits, top level integration and verification, bench characterization, and mentoring.Circuit Design Responsibilities Low Noise VGA/PGA, peak/power detector, GM-C filters,continuous time sigma-delta ADC, current-steering and R-2R DAC, image filter, analog video (meeting CVBS standards) driver, PLL (VCO/DIV), open-loop/closed-coop control for offset correction, common-mode, and gm-C tuning.Other ResponsibilitiesIdentifying and minimizing spurs in supply/ground, in PLL and ADC, LDO design, padring design, and fixing EFR issue.Consulted for foundry business on analog component for Dongbu Hitek high-performance HP180nm analog/mixed-signal/power process release and general high-performance analog circuit/product practice.

Project lead for high-speed (>1MHz) and high-resolution (16-Bit to 24-Bit) oversampled ADCs. Successfully developed and released 8 industry's leading oversampled ADCs. Also experienced in designing several high-speed pipeline, successive approximation (SAR) and cyclic ADC products. Mentoring designers and application engineers. One of the initial designers who created TI's high-speed high-resolution oversampling converter product line. Selected released products: ADS1672, ADS1675, ADS1601, ADS1602, ADS1605, ADS1606, ADS1625, ADS1626, ADS129X.Consistantly building technical capability in the field of high-resolution and high-speed oversampled ADC within the company to strenghten its technical leadership, product portfolio and increase market share. Elected to Member of Group Technical Staff of TI technical ladder in 2005.Specialties: ADC product development, hands on design, architecture modeling, product definition, layout, characterization, and application, mentoring and team building. Yield/reliability improvement and failure analysis.Innovation resulted in 4 US patents, 1 disclosure and 7 publications.