Leading a global team which will involve following several tasks: a. Involving the latest design; b. Addressing NAND-related issues reported by customers; c. Providing internal MT/Qualification support, like FA support/CA development

Programs include new development or porting of different IPs to different foundry process technology nodes(40nm~14nm) and manages IP development for key programs and successfully executes the programs against established commitments.

As a member of design team, mainly jobs are as follows:1. Leading a SRAM(128Mb/10ns) design within NAND2. ROM/REM/EREM design3. Data Path design(LPDDR3-1.6Gbps/LPDDR4-2.4Gbps):4. Co-sim modeling based on Synopsys's MIX-Signal Solution5. Define fullchip level performance check list and run the simulation ;6. Enable EV/SOA check function based on XA

Working as an mix-signal design engineer, responsible for the development and implementation for BG/REG/VDT/PSW which will cover the process from 0.18um to 28nm

as a part of the member I have experienced NOR/NAND/PCM project , mainly jobs is to building fullchip model and run fullchip simulation, root cause the issues and find solution:1. Pre-verification (07/2011~01/2013：NOR 1G/512M 45nm) Maintain mix-signal fullchip model: 2. Schematic design(01/2013~01/2014 nor & pcm) 3. 01/2014~07/2015 (2D/3D NAND)This is a transition for our site and this produce is “new” for almost of us, so we take a lot time to do pre-work;