Will Arthur Email & Phone Number

Santa Clara, California, US

Still figuring it out, but will be helping to lead development of BIOS security related modules.

Herndon, Virginia, US

Develop C and Python cyber security code

Cyber security development. Automated test development. Network development. Reverse engineering of firmware and software. Python, C, and assembly on Linux and Vxworks.

Arlington, VA, US

• Developed TPM (Trusted Platform Module) 2.0 software stack to enable internal development. The code automates HMAC and encryption session management tasks and vastly eases application development. Architected the code.
• Provide TPM 2.0 consulting and design expertise to internal projects across the company.
• Architected and developed TPM 2.0 code for low level firmware running on a Xilinx ASIC.
• Represent and advocate for Raytheon in Trusted Computing Group industry standards organization. One example: secured a block of reserved NVRAM addresses for Raytheon use.
• Helped finish TPM 2.0 code for a hardened Linux kernel. Found and fixed many sources of intermittent errors, kernel crashes, and seg faults. Also used Coverity to find and fix bugs.
• Developed C code to setup and communicate to a Postgres SQL database as proof of concept for a future project.

Santa Clara, California, US

• Sr. Staff Firmware Engineer/Technical Leader, Intel Corporation, Columbia, SC, 3/2007 – present.
• I volunteered to fill a gap 9 years ago as the single Trusted Execution Technology (TXT) developer. With very little supervision and assistance during the first 3 or 4 years, I learned the technology, wrote all the.
• My team of 12 people designs server security features, specifically TXT and Boot Guard authenticated code modules (ACMs) and related BIOS code. TXT and Boot Guard enable hardware-based security features in Intel CPUs.
• I wrote two industry specifications for TSS (TPM Software Stack) 2.0 and the open source code to implement those specifications: https://github.com/01org/TPM2.0-TSS. This software allows Intel and other industry.
• The TPM 2.0 specification is very challenging to understand. To solve this problem, I wrote a book proposal, successfully pushed it through the approval process, and pulled together a team of 2 authors besides myself.

Santa Clara, California, US

• Senior BIOS Engineer, Intel Corporation, Columbia, SC, 11/2004 – 3/2007.
• Coded and debugged silicon validation BIOS for south bridge and north bridge server chipset components. Worked closely with silicon validation engineers to debug silicon issues and develop workarounds.
• Optimized memory initialization code, resulting in a 50% speed increase, while implementing fully buffered DIMM (FBD) memory initialization code for a server north bridge chipset.
• Prototyped an innovative coding and process improvement strategy for the entire BIOS group that allowed multiple teams and projects to reuse and share code, resulting in a huge efficiency boost and much more robust code.
• While developing BIOS features, I also implemented regression tests for chipset BIOS code and memory reference code. My goal was to avoid “going backward”, i.e. breaking code that was previously working.

Santa Clara, California, US

• Developed pre- and post-silicon validation tests for graphics subsystems in Intel chipsets (specifically secure graphics), automated build and regression process for graphics validation tools, and wrote a Linux.
• Created anti-debug solutions to inhibit reverse engineering of digital rights management (DRM) software.
• Modified Linux CDROM device drivers, wrote Perl scripts to obfuscate the symbolic information in ELF binaries, maintained the DVD content scrambling system (CSS) code base, and debugged timing related problems between.
• Developed and debugged the Standalone Configuration (SAC) utilities used to configure Intelligent I/O® (I2O) subsystems. Ported a Unix HTML browser to DOS. Developed a modified CGI interface to enable communication.
• Designed Perfmon, an Ixworks device driver that extracts I/O bus performance statistics from performance monitoring hardware in i960® RX processors. Created a software simulation of the i960 performance monitoring.

Ported kernel routines of the VRTX RTOS to the i960 processor family.Performed validation testing of the AMD29000 port of VRTX.

Developed firmware for in-circuit emulators for RISC processors, with special emphasis on execution control, trace disassembly, and silicon errata workarounds.After previous efforts failed to correctly implement the trace disassembly code for the AMD 29200 processor, I redesigned this code from scratch so that it performed trace disassembly accurately for.

Engineering Bscs

Associate Degree, Electronics Technology