William Bates Email & Phone Number

El Segundo, California, United States

Manhattan Beach, California, United States

• FPGA Design Engineer
• Responsible Design Engineer for a complex demultiplexing system consisting of 4 Xilinx Virtex UltraScale+ FPGAs
• Designed and implemented new functionality into largescale design to meet strict customer requirements
• Used various debug techniques including testbenches, ILAs, packet sniffers and custom scripts
• Used best practices to close timing across multiple FPGAs through pipeline, fanout and clock domain crossing techniques
• Provided design and hardware recommendations to program leads with similar system level goals

Boulder, Colorado, United States

• Wrote code in C++ to process data streams and store in Google Protobuffers (GPBs)
• Containerized proprietary software using Docker and Podman for handoff to customers
• Led coordination efforts with multiple companies, resulting in a successful handoff

Baltimore, Maryland Area

• FPGA Design Engineer
• Brought up and configured the HPS on a Stratix 10 FPGA to peek and poke registers from U-Boot
• Instantiated Intel 40 GbE MAC and integrated into an RDMA Engine for RoCEv2 traffic of OCS VITA 49.2
• Designed and stood up a lab for FPGA testing including, parts research, BOM management, and lab procedures
• Followed processor programming procedure and conducted acceptance testing on Line Replaceable Units (LRUs)

Nashua, New Hampshire 03053

Baltimore, Maryland Area

FPGA Design/ Test Engineer

Baltimore, Maryland Area

ASIC Design Engineer - RTL Designer

Pittsfield, Massachusetts Area