William Shu Email & Phone Number

San Francisco Bay Area

Advisor to Founder and Executives at startups. Subject matter consultant on software development, product design and application support.

Mountain View, Ca

Partnered with internal and external customers to deliver new technology and process in order to satisfy customers’ need and create value for their business.• Collaborated with key automotive semiconductor customer, establishing software quality assurance (QA) and testing improvement process. • Led cross functional / product teams and developed full incremental ECO flow on digital design platform including physical implementation, parasitic extraction and timing/power, improving full flow TAT (turnaround time) by 2X while maintaining overall QoR (quality of results).

Mountain View, Ca

Managed development of Synopsys signoff products, technology roadmap, and solutions. Worked with product development, product marketing, application engineering, and business development to define technical product release requirements and strategy to grow customer base. Acted as main R&D liaison with customers including all PrimeTime accounts in Japan regions.• Drove customer collaboration on key STA technologies development for each critical technology node, removing technical challenges and achieving timing signoff success with efficiency. • Managed research and creation of PrimeTime ECO technology which include simultaneous multi-scenario timing / DRC fixing and total power recovery, accelerating product license / revenue growth with major differentiators.• Oversaw research and creation of SMVA (simultaneous multi-voltage aware analysis) technology for low power designs, enabling users to reduce the hardware resources and turnaround time for multi-scenario analysis, while maintaining signoff quality timing correlation. • Led development of advanced analysis features in deployed PrimeTime software suite releases such as:o Waveform propagation, Library scaling, Variation STA (AOCV/POCV), Hierarchical STA (ETM, ILM, HyperScale), Mode merging and Galaxy constraint analyzer • Built and coached high caliber teams of R&D managers and software developers, improving productivity and motivating individuals to innovate and perform to potential.• Established PrimeTime as industry’s de-facto gold standard for gate-level static timing analysis by conducting continuous technological innovation, software performance / capacity / quality improvement and customer success management.

Mountain View, Ca

Guided PrimeTime SI and Delay Calculation teams to provide broad-based technical leadership and product direction, identify opportunities to further technical innovation and product competitiveness, drive definition and delivery of market-leading solution, and establish standard for the industry. • Oversaw development of CCS (Composite Current Source) technology for PrimeTime SI, part of open-source Liberty library modeling standard, enabling accurate and comprehensive modeling of nanometer effects.• Managed research and development of advanced SI timing window alignment technology and path based SI analysis, reducing excess analysis pessimism and avoiding unnecessary design iterations due to over-fixing and over-constraining design implementation.• Directed development and deployment of static noise analysis, enabling detection, analysis, and avoidance of potential chip functional failures due to noise glitches on nets that should not be switching.

Mountain View, Ca

Led activities of R&D team working on design, development, troubleshooting, and debugging of new software product integrating static timing and crosstalk analysis in a single, streamlined, comprehensive and accurate analysis package.• Led and drove successful technology partnership with key customers on signal integrity analysis by improving designer productivity and speeding design closure with new product solutions. • Conducted development and successful launch of PrimeTime SI product line, addressing growing challenge of detecting and resolving crosstalk on deep submicron system-on-a-chip (SoC) designs.

Sunnyvale, Ca

Responsible for FPGA (Field-Programmable Gate Array) architecture reserach, design and software suite development.• Successfully designed and productized FPGA architecture for multiple antifuse based product families.• Designed and developed FPGA programming, verification testing, channel segmentation routing, extraction and timing analysis software, improving performance and resource usage of FPGA.