ASIC Verification

Test planning, feature extraction and testbench development at the block & device level including both in-house agent creation and VIP utilization, hierarchical UVM Register Layer model creation, functional coverage model generation, test and sequence development and the work to close all coverage. The whole nine yards.

Contract Design Verification. This job is a third generation large ASIC verification using System Verilog and UVM to create object-oriented, constrained random testbenches. As part of a small team, I wrote many UVC agents and environments that included the UVM register layer for both block and top level testing, assertions for protocol checking and cover properties for correctness coverage. I used Synopsys VCS and Verification Planner (HVP) for feature list management and tracking verification progress in a coverage (code & functional) driven environment. I used the same toolset and approach to verify an FPGA that provides support functions to the ASIC including writing an ARM AXI4 Agent. Conditional coverage closure was done at 100% including exclusions using formal methods plus Certitude fault analysis. I was peripherally involved in the DFT sphere where I did DV on the test hardware and ran/debugged the Modus testbenches. Using git/gerrit/Jenkins for revision control and a home grown, python based build system.

Large FPGA constrained random verification using System Verilog OVM and UVM

Contract Design Verification. ASRG program: http://solarsystem.nasa.gov/rps/asrg.cfm. Verification of spacecraft power source control logic including Mil-Std 1553 bus and other proprietary interfaces. Large Actel RTAX-S FPGA verification using Mentor QuestaSim, System Verilog and OVM. Part of a team doing object oriented, requirement/feature list based, constrained random testbench development including work on the environment, interfaces, agents, drivers, monitors, sequencers, sequences, prediction, coverage, assertions and test cases. Subversion for SCM.

Integration and verification of large IP blocks into very large computing device.

Large ASIC verification using System Verilog to create object-oriented, scenario based, VMM compliant constrained random testbenches. Includes RAL & VMM_SB. Synopsys VCS and VMM Planner for feature list management and tracking verification progress in a coverage (code & functional) driven environment. Perforce for SCM.

Worked briefly linting a VHDL design for an Intrinsix client. I used the Cadence NC-VHDL compiler and their HAL Lint tool. Generated a detailed report with prioritized recommendations for needed changes.

Worked on Infineon’s next generation Software Defined Radio (SDR) wireless baseband ASIC. Quickly learned the architecture of the device central control block (DIGRF). Prepared a feature/requirements list from a specification. Evaluated verification methodologies and recommended a solution based on time and resource limitations, design complexity and existing DV infrastructure (both SV and VHDL/C). Wrote the first directed test case and then transitioned to construction of a fully functional, predictor, monitor and scoreboard written in VHDL and dedicated to control messaging DV.

Assignment: Mercury Computers (1/09-4/09) – Convert a legacy testbench to OVM, expand RapidIO C-model/System Verilog (SV) testbench interface using DPI, add SV coverage and scoreboard. Simulator is Mentor QuestaSim w/C-debugger. Customer interface for two other engineers doing work on the same contract. Wrote intro doc to minimize environment learning curve.Assignment: Nortel Networks (6/08-12/08) – New test case generation, existing test case debug (regression), infrastructure creation and debug in an existing, constrained random DV environment consisting of single and multiple large FPGA testbenches all written in System Verilog using Synopsys’ VMM and simulated using VCS. Interfaces: SPI4.2, PCIe, GigE, amongst others. Wrote a register description post-process PERL script. This Nortel group uses CVS for SCM.Assignment: Mercury Computers (3/08-5/08) – Created a new, constrained random, self-checking, reusable testbench architecture and implementation incorporating legacy user interfaces (customer) utilizing QuestaSim and System Verilog under OVM for an FPGA based system on chip design. I wrote the TB front end (OVM Agent), global transaction class and complete OVM demo including TLM channels, factory test and object generation and doc for same. I also converted directed tests for a legacy env. Mercury uses Clearcase for SCM

Contract Design & Design Verification (DV). I wrote the architecture specification for an ARM AMBA AHBL external memory controller (EMC) block including block diagrams (Visio), text, requirements, timing (TimingDesigner) and external device research. I also wrote the verification specification (test plan) for the EMC and a single highly configurable VHDL testbench that can randomly simulate hundreds of different external memory configurations under the control of a TCL script and passed generics. I wrote the verification specification for an AHBL embedded SRAM control block and performed the DV (ModelSim) using a complex internal tool consisting of AHBL bus functional models (BFM) and a compiled control script. I managed the BFM verification models locally using both CVS and SVN revision control (SCM) tools.

DESRES was/is designing and building an application specific, massively parallel supercomputer system for performing “molecular simulations involving proteins and other biological macromolecules of potential interest from both a scientific and a pharmaceutical perspective*”. I performed verification on a block level design that connects various system blocks using a complex control scheme and a local memory. I used Synopsys VCS-NTB (Vera), RVM, and a proprietary, non-cycle accurate reference model (C++) that is also part of the machine architectural simulator. I wrote a complete, constrained random, self-checking NTB testbench (transaction classes and classes for generators, drivers, monitors, scoreboard, and a memory controller) for this block complete with code coverage, functional coverage and System Verilog assertions. I also extracted features from the block specification that are the basis for the functional coverage. Used Perforce for SCM.*www.deshawresearch.com

CNT manufactured Fibre Channel switching equipment for the Storage Area Network marketplace. As a Principal Engineer and technical lead, I headed a DV team tasked with the verification of a multi-million gate ASIC. I revamped the base infrastructure to better integrate the configuration management tool (PVCS) and simulation environment, which consisted of Verisity Specman and ModelSim running on a Linux multiprocessor platform. I was the LSF administrator and dealt directly with Platform. I wrote several scripts that implemented and automated a regression environment and completed a test plan document to guide the verification and completion of the device. I also converted and upgraded several first generation e language tests to this second generation project. CNT was purchased by McData in June of 2005. McData have since been purchased by Brocade.

SGI is a multi-discipline hardware and software developer as well as a services provider. As an MTS Technical Lead, I was responsible for large ASIC system design verification in the Servers and Processors group (SPG).Lead role on a multi-geo team tasked with the DV of a large ASIC device.Tools: Synopsys VCS for simulation of Verilog RTL. Raven (SGI EDA) C++ testbench automationWrote the System Verification Plan for the ASIC. Wrote and ported many diagnostics using the Raven testbench environment.PERL scripting that used commands from Perforce to analyze, report on and offer solutions to problems concerning a user’s client view of the design depot.Led half an evaluation team contemplating the best course for future verification efforts at SGI - replacing Raven with one of Verisity Specman or Synopsys Vera.Did research and gathered information that I used to document a complex device/system reset mechanism.

Principal Consulting Engineer: technical support of sales, program management, and direct design/verification engineering.MultiLink Technology Corporation – Project Leader for a 13 person team - design & verification of a OC-192 SONET device.Agere Systems – Specified the architecture for an InfiniBand (IB) Plugfest Evaluation System.Enikia Corporation (now Arkados) – Given an Enikia architectural document, our team specified a design, verification and test environment for an SoC ASIC.Agere Systems – Specified and wrote an ARM AMBA ASB protocol checker using the ‘e’ verification language, Verisity’s Specman & ModelSim.Telcordia Technologies – Designed, synthesized and verified a BRAID1 and BRAID2 Encipherment circuit for PACS Radio Port Control Unit (RPCU) handling eight simultaneous full-duplex calls. VHDL, Renoir, Modelsim, Leonardo for Altera Flex10K.