Led integrated circuit development for a novel, highly-differentiated deep learning accelerator.

• Designed, taped-out, and tested multi-GHz data converters for mmWave beamforming transceivers• Led team in early adoption of advanced-node fabrication process from a major foundry• Managed interface with IP, EDA, and foundry vendors for entire RFIC team; accelerated product development by quickly and assertively resolving problems with suppliers• Co-designed systems with external teams• Participated in frequent interviews for new hires

• Designed, fabricated, and tested a multiplexed, highly-digital, large-scale neural front endrecording prototype in 65nm CMOS• Instructed a large undergraduate course on frequency domain circuit analysis; managed ateam of four teaching assistants and graders• Developed and instructed a special topics course on data converters• Designed, fabricated, and tested ultra-low-power, low-voltage AFE for ECoG, 11-bit SARADC, and 8-bit asynchronous SAR ADC with 10 fJ/conv-step FOM in 65nm CMOS• Designed digitally-compatible TDC-based supply monitoring scheme for high-precision,high-frequency supply voltage diagnostics• Managed group tapeout efforts for multiple highly-integrated and multi-project systems• Developed infrastructure for batch-mode system-level AMS simulation using both Mentor(AFS) and Synopsys (XA, VCS) tools• Developed Python-based test automation using NI-DAQ platform• Mentored Undergraduate, Masters, and junior Ph.D. students

• Designed analog and digital circuits for the Integrated Neural Interface (INI) project including on-chip rectifier, low-dropout regulators, clock and data recovery, and chip-level digital control scheme• Solved specific problems related to robust transmission of system control data over an active inductive power link• Developed LabView-based GUI for insect telemetry IC

• Maintained ownership of a product family and all all related tasks including characterization of sort failures, analysis and improvement of the fabrication process, product robustness, and disposition of anomalous material • Performed yield analysis for volume ramp of 65nm technology, improving the design, process, and test methodology to increase yield • Developed and presented product updates for large meetings with fab-wide audiences • Analyzed 65nm metallization process to improve yield by defect reduction • Developed statistical software tools for fab defectivity• Designed automated robustness characterization software • Developed a website that served as a clearinghouse for a wide variety of device related information, including aggregated statistics on fab and post-package yield information • Developed and managed data collection and storage systems for two separate facilities in Aizuwakamatsu, Japan and Austin, TX