-Ran DRC & LVS for in-house developed IPs such as analog block, temperature sensor, isolation cells and third-party IPs such as PLL, MPHY, single-port SRAM, 2-Port register SRAM, rom, and One-Time-Programmable (OTP) memory to facilitate chip-level integration.-Performed LVS for multiple ASIC tape outs in 90nm, 65nm, 40nm, and 28nm and improved process of full-chip LVS.-Completed 40nm-to-28nm process migration for in-house IPs (macro with programmable delays and glitch filter) with synthesis, functional simulation, STA, place & route, RC parasitic extraction, and circuit simulation.-Worked with IP development team to generate LEF view and resolve issues in logic modeling & mismatches among EDA views, foundry team to debug physical verification issues due to rules deck.-Performed functional verification for memories generated by third-party memory compilers & internally developed macros.-Resolved ASIC library issues and provided workaround to continue efforts in ASIC development without delay impact on project schedule.-Managed timely library release for design projects across different design centers: Milpitas, US, Bangalore, India, and Omer, Israel.

-Verified functionality between logic model and transistor level model using Timemill, and logic simulation with back-annotation of standard delay file (sdf).-Performed design conversion by mapping customer’s FPGA design into target library cells using Design Compiler, performed pre-layout and post-layout static timing analysis using Primetime and dynamic simulation using Verilog XL and NCVerilog, fault coverage using Verifault, Flex Test and Hyperfault.-Implemented a procedure to correlate the critical path delays reported from Astro, Apollo, and Primetime, using Hspice.-Provided support for the Synopsys Design Compiler library, verilog simulation model, and Mentor FastScan library.-Generated Synopsys Apollo library for foundry specific 0.18u processes, “UMC 0.18u” and “1st Silicon”.-Developed a Magma library for CSM 0.18u and UMC 0.35u.-Generated IBIS model for general purpose IO.