William Harrell Email and Phone Number
William Harrell work email
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William Harrell personal email
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With over 14 years of experience in FPGA design and architecture, I am a Senior FPGA engineer at Blue Origin. I am passionate about creating innovative and reliable solutions for complex systems and challenging applications.I have led and contributed to multiple FPGA projects across different domains, such as a custom 10G Ethernet switch, a Cyber-security system controller, and a high speed packet generator. I have also mentored junior engineers, modified UVM testbenches, and created and streamlined project build scripts. I have a strong technical background in hardware integration, troubleshooting, and RTL. I am always learning and expanding my skills and knowledge in FPGA and hardware engineering.
Lockheed Martin
View- Website:
- lockheedmartin.com
- Employees:
- 101322
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Staff Asic And Fpga EngineerLockheed MartinDenver, Co, Us
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Senior Fpga EngineerBlue Origin Jun 2024 - PresentKent, Wa, Us -
Staff Asic/Fpga EngineerLockheed Martin Apr 2022 - May 2024Bethesda, Md, Us• Architecting and leading development new Cyber-Security FPGA.• Mentoring junior engineers.• Requirements creation and derivation
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Senior Asic/Fpga EngineerLockheed Martin Jan 2020 - Apr 2022Bethesda, Md, Us• Created new project baseline and TCL scripts for CI. • Led UVM team of 2 junior engineers.• Modified 3rd party UVM testbench predictor, coverage, and environment classes.• Created new sequence and test classes• Created detailed verification plans to meet functional coverage• Technical point of contact for 3rd party contractor for UVM project.• Led RTL code reviews and FPGA technical reviews.• Custom Ethernet switch FPGA with 10GE and 10/100/1000 Ethernet• Redesigned packet filter module to meet new requirements.• Designed new configuration module for device configuration while reducing boot time.
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Senior Fpga/Hardware EngineerSerialtek Jun 2018 - Oct 2019Longmont, Colorado, Us• Designed and architected multi-purpose FPGA (Xilinx US+ZYNQ MPSOC) that contains a LCD controller module, SMBus/I2C capture module, IO expander module, and a custom ZYNQ register interface.• Created SystemVerilog testbench for multi-purpose FPGA.• Created new memory format for SMBus/I2C capture• Debugged RMAs and manufacturing defective boards -
Engineer (Fpga Engineer)Ultrata Llc Jul 2016 - Jun 2018• Designed custom DDR memory PHY using Xilinx Ultrascale+ IO primitives. • Designed FPGA utilizing PCIe, IBERTs, and Interlaken for board check out. • Created self-checking testbench and Python post-simulation parsing script.
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Electronics Design Engineer 2Viking Enterprise Solutions May 2014 - Jul 2016San Jose, California, Us• Designed system architecture for a disaggregated server enclosure for NVMe over Fabric.• Designed FPGA using I2C to gather HDD status and control in JBOD• Designed FPGA for a dual socket Xeon based server power sequencer• Hot fixes for legacy FPGAs• Xeon server validation, bring-up, and integration• Created FPGA design guidelines and coding standard documents• Mentored Engineering Interns and others in FPGA design and debug -
Test System Design Engineer (Fpga Design)Seakr Engineering, Inc. Jul 2011 - May 2014Centennial, Colorado, Us• Hardware architecture for COTS based high-speed test platform.• Designed FPGA for packet traffic generation across multiple channels across multiple sRIO ports with aggregate bandwidth of 36Gbps. Utilized 1G UDP/IP for traffic generator configuration.• Designed FPGA for packet checking; syncing data then processing packets by deinterleaving then Reed Solomon decoding (Xilinx IP) packets for in hardware comparison.Updated legacy FPGA to new requirements for project reactivation -
Hardware Developement EngineerSmart Modular Technologies Jan 2010 - Mar 2011Newark, Ca, UsDesigned VHDL blocks for FPGA SSD Controllers:• Integrate SATA IP• Data transport enhancement and optimization• NVRAM Interface• Created FPGA design environment for development board utilizing NAND Flash, SATA, DDR2, internal data transport, and NVRAM interfaces• Hardware validation of NVDIMM -
Hardware EngineerComtech Ef Data Oct 2007 - Oct 2009Chandler, Az, Us• Designed FPGA to control DACs, ADCs, and digital synthesizers via a 3-wire interface • Designed FPGA to control new M:N redundancy system• Designed 12 Port Ethernet switch card for use with legacy products -
Nreip InternNaval Research Laboratory Jul 2005 - Aug 2005Designed “Dead Man” switch circuit for engine cut off of an autonomous boatDeveloped Navigation and Guidance algorithm in MATLAB to be used for an Underwater Unmanned Autonomous Vehicle (UUAV)
William Harrell Skills
William Harrell Education Details
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New Mexico State UniversityElectrical Engineering
Frequently Asked Questions about William Harrell
What company does William Harrell work for?
William Harrell works for Lockheed Martin
What is William Harrell's role at the current company?
William Harrell's current role is Staff ASIC and FPGA Engineer.
What is William Harrell's email address?
William Harrell's email address is wi****@****ail.com
What schools did William Harrell attend?
William Harrell attended New Mexico State University.
What are some of William Harrell's interests?
William Harrell has interest in Weightlifting, Cooking, Soccer, Snowboarding, Mountain Bike Riding.
What skills is William Harrell known for?
William Harrell has skills like Fpga, Xilinx, Electronics, Debugging, Vhdl, Testing, Hardware, Hardware Architecture, Lattice, Modelsim/questasim, Embedded Systems, Active Hdl.
Who are William Harrell's colleagues?
William Harrell's colleagues are Manuel Perea, Lisa Ball, Michael Giacona, Victor Cruz, John Scherschel, Sam Stout, Jacqueline Gedney.
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