William Harrell Email & Phone Number

Denver, Co, Us

Kent, Wa, Us

Bethesda, Md, Us

• Architecting and leading development new Cyber-Security FPGA.• Mentoring junior engineers.• Requirements creation and derivation

Bethesda, Md, Us

• Created new project baseline and TCL scripts for CI. • Led UVM team of 2 junior engineers.• Modified 3rd party UVM testbench predictor, coverage, and environment classes.• Created new sequence and test classes• Created detailed verification plans to meet functional coverage• Technical point of contact for 3rd party contractor for UVM project.• Led RTL code reviews and FPGA technical reviews.• Custom Ethernet switch FPGA with 10GE and 10/100/1000 Ethernet• Redesigned packet filter module to meet new requirements.• Designed new configuration module for device configuration while reducing boot time.

Longmont, Colorado, Us

• Designed and architected multi-purpose FPGA (Xilinx US+ZYNQ MPSOC) that contains a LCD controller module, SMBus/I2C capture module, IO expander module, and a custom ZYNQ register interface.• Created SystemVerilog testbench for multi-purpose FPGA.• Created new memory format for SMBus/I2C capture• Debugged RMAs and manufacturing defective boards

• Designed custom DDR memory PHY using Xilinx Ultrascale+ IO primitives. • Designed FPGA utilizing PCIe, IBERTs, and Interlaken for board check out. • Created self-checking testbench and Python post-simulation parsing script.

San Jose, California, Us

• Designed system architecture for a disaggregated server enclosure for NVMe over Fabric.• Designed FPGA using I2C to gather HDD status and control in JBOD• Designed FPGA for a dual socket Xeon based server power sequencer• Hot fixes for legacy FPGAs• Xeon server validation, bring-up, and integration• Created FPGA design guidelines and coding standard documents• Mentored Engineering Interns and others in FPGA design and debug

Centennial, Colorado, Us

• Hardware architecture for COTS based high-speed test platform.• Designed FPGA for packet traffic generation across multiple channels across multiple sRIO ports with aggregate bandwidth of 36Gbps. Utilized 1G UDP/IP for traffic generator configuration.• Designed FPGA for packet checking; syncing data then processing packets by deinterleaving then Reed Solomon decoding (Xilinx IP) packets for in hardware comparison.Updated legacy FPGA to new requirements for project reactivation

Newark, Ca, Us

Designed VHDL blocks for FPGA SSD Controllers:• Integrate SATA IP• Data transport enhancement and optimization• NVRAM Interface• Created FPGA design environment for development board utilizing NAND Flash, SATA, DDR2, internal data transport, and NVRAM interfaces• Hardware validation of NVDIMM

Chandler, Az, Us

• Designed FPGA to control DACs, ADCs, and digital synthesizers via a 3-wire interface • Designed FPGA to control new M:N redundancy system• Designed 12 Port Ethernet switch card for use with legacy products

Designed “Dead Man” switch circuit for engine cut off of an autonomous boatDeveloped Navigation and Guidance algorithm in MATLAB to be used for an Underwater Unmanned Autonomous Vehicle (UUAV)