William Peters Email & Phone Number

Sunnyvale, California, Us

Mountain View, California, Us

Fort Lauderdale, Fl, Us

PCBA failure analysis for lidar and automotive sensor and control systems. Antenna test data analysis.

Designed and validated high-speed electrical interconnects for fiber optical transceiver technology including 400GBASE-D/FR4, 100GBASE-DR1 and others. Designed PCB interconnects, electrical connector and component footprints and optical sub-assemblies for signal and power integrity using EM and channel simulation. Validated SI design with VNA, TDR and BER/TDECQ. Troubleshot and debuged design, manufacturing and field issues related to the electrical interconnects.

Santa Clara, California, Us

● I/O-centric signal integrity design for high-speed serial interfaces in Intel’s internal Hard-IP SIPI organization; high-speed serial interfaces include 10GBASE-KR, PCI Express Gen 2 & 3, USB3, USB3.1, SATA3, HDMI, and others. ● Leveraged technical expertise to debug critical post-silicon issues, solve pre-silicon design challenges, and aid customers with debugging simulation issues. ● Directed SI and modeling methodology development across the team and conducted company-wide signal integrity training at several sites.● Specified and conducted pico-probe VNA measurements of active device input impedance and device compliance.● Developed plan and electrical validation board architecture to evaluate backplane, and zSFP+ and zQSFP+ module applications for a 25G PHY design.Key Achievements● Designed a configurable test-board set with over 10,000 possible channels to support PHY design targeting and development, post-silicon validation, and spec pathfinding. Lead engineer with primary role in concept, design, implementation, fabrication, parts, assembly and testing. The test system is widely used in design and validation roles across Intel.● Built up a new high-speed team from scratch, mentoring new engineers, incorporating best-known methodologies and processes, and developing new methodologies to support the team goals and objectives.

Santa Clara, California, Us

● Key contributor for the signal integrity design of DDR3 1333-1600 leading directly to changes in JEDEC spec, and the I/O, package and PCB design guidelines for Intel chipsets. Completed early pathfinding work on DDR4.● Developed an efficient automated massive simulation approach to evaluate signal integrity of DDR3 signal groups across high volume manufacturing conditions. Key Achievements● Developed an innovative impedance matching design for command/address on DDR3 1333 which has been adopted into the JEDEC specification and used in the reference DIMM design.● Contributed to the first successful DDR3 1333 and 1600 memory controller implementation at Intel, which established a long-standing technical benchmark.● Assumed technical responsibilities of three former team members during a staff reorganization and completed the project successfully with reduced resources. Overcame crosstalk challenges due to the new form-factor and completed the SI analysis for the DDR3 on the first MCP integrated memory controller.

Us

● Led the electrical modeling, signal integrity analysis, and related methodology development for high-speed serial (SERDES) interfaces in communications devices and platforms. ● Recommended package, I/O, and platform design guidelines. ● Contributed to the development of the IEEE 802.3 Backplane Ethernet channel specification as a key member of the 802.3ap Task Force.Key Achievements● Original member of a new signal integrity team tasked with providing SI and package design support for Intel's high-speed communications devices. Developed and evaluated new methodologies for modeling channel components and performing channel simulation.● Designed and developed an extensive set of test channels known as ‘Peters channels’ which were used to develop the Backplane Ethernet channel informative spec (IEEE 802.3 annex 69B). The models have been adopted as an industry standard used throughout the industry and academia for developing 10G-KR PHYs and for subsequent spec developments.

Developed a sensor that measures the thickness of connective tissue growth on a material substrate using a current-driven electrode array. Analyzed the electric/current fields using custom method of moments code and ANSYS finite elements software and correlated to in vitro measurements. Synthesized and examined the swelling characteristics of Biospan / poly(ethylene oxide) blends.

Developed polymer membranes for use with transdermal drug delivery systems. Utilized differential scanning calorimetry, high pressure liquid chromatography, gas chromatography and dissolution testing.

M.S., Bioengineering

B.S., Biomedical Engineering