William Schubert Email & Phone Number

Falls Church, Va, Us

Northrop Grumman Mission Systems Sector - Digital TechnologySupport ASIC and FPGA product development by working closely with designers and perform constraint-random functional verification on designs using current industry verification methods, tool, and techniques. This includes using SystemVerilog, SVA, UVM, and third party VIP to develop constraint-random verification environments to generate and send stimulus to the DUT, check for correct DUT behavior, and collect functional and code coverage metrics to determine verification completeness. Verification planning, test case development, regression running, fault analysis and RTL debug.

Responsible for the development of three ethernet 100G verification environments using Cadence Ethernet VIP to verify ethernet design which incorporates Synopsys ethernet IP. One environment for the PCS, one for the MAC, and one for the ethernet top which consisted of both MAC and PCS. Due to Synopsys proprietary MAC interface, developed a custom interface to convert for it to Cadence VIP.

San Jose, Ca, Us

Worked on a small team of verification engineers to develop from that SATA and L2 specification verification plans for the transport and command layers of the SATA protocol. Help to develop functional coverage plans using a new in-house format. Worked to analyze and determine how old legacy testbench were built, how they worked, what tests were developed and what the coverage holes were. These legacy testbenches were develop years ago and had no documentation, thus the need to examine and evaluate them. Implemented new SATA DUT features in Specman testbench. Required analyzing the L2 specification to determine what and how the new RTL feature worked and then implement and integrate new testbench behavior to check correct DUT behavior of these new features. Then implement and close functional coverage of these new features.KEY ACHIEVEMENTS:** Successfully modified testbench behavior and checkers to implement new SATA DUT features ending in successful tape out in August 2015.** Successfully developed functional coverage plans for SATA transport and command layers

San Jose, California, Us

Work with Sales team to provide customer education, training, tool installation, licenses, and support on Coverage Driven Verification (CDV), Metric Driven Verification (MDV), e Reuse Methodology (eRM), Open Verification Methodology (OVM), and Universal Verification Methodology (UVM). Tools include Incisive Enterprise Simulator, which includes Specman Simulator, IUS, Enterprise Manager (eManager), and Enterprise Planner (ePlanner). Expert knowledge of Specman e language and general knowledge of SystemVerilog (SV). Supported various semiconductor companies from the large to the small. Performed numerous Verification Project Launches (VPLs) where a basic functional verification environment is designed for the customer and verification plans are created from the design specification. Typical VPLs can last from two weeks to 3 months and may or may not include the use of Verification IP (VIP). General knowledge of the following VIP protocols: PCIe Gen2/Gen3, USB2.0/3.0, Ethernet, AHB, and AXI. Also experienced with migrating VMM environments from running on VCS to Incisive (ncsim / IUS). Provide support for customer in debugging Cadence Verification tools and be liason between customer and Cadence R&D. Provide internal support for the testing of new Cadence verification tool releases.KEY ACHIEVEMENTS:** Successfully supported numerous customer engagements** AE of the Quarter, Q3, 2007** Received 13 Recognition Awards** Put together and delivered several public workshops on functional verification

Independently drive functional verification effort of 802.15.3 UWB MAC design. Educated Management and Designers about functional verification challanges and current industry methodologies. Responsible for development and execution of functional verification plan, coverage metrics, and test suites. Hired and worked with two consultants to develop MAC Specman testbench using e language and PCI and AHB eVCs within 11 months. Developed internal custom eVCs. vManager used for regression runs and test anaylsis. Successful tape-out in November 2005. ATE support on post silicon included vector generation and execution on Teradyne Catalyst. Researched ways to perform both MAC and Digital Baseband (DBB) verification and MAC - DBB - RF (digital - analog) verification.KEY ACHIEVEMENTS:** Successfully developed initial test plan and test benche for 802.15.3 MAC verification program.** Developing test bench using eVCs and eRM methodology .** Effective use of Specman Elite. ** Successful demo-chip tape-out, November 2005.

Geneva, Switzerland, Ch

Design Engineer III, AST Division (12/2003 to 11/2004)Independently design microarchitecture of shifting register file. Design new co-processor core utilizing shifting register file and IP. Design and verify microarchitecture. Design verification environment using Specman Elite and the ‘e’ language. Maintain documentation using framemaker. Maintain revision control using CVS. Synthesis with Design Compiler. Regression run, bug tracking, and bug correction.Design Engineer III, AST Division (6/2003 to 12/2004)Independently drive functional and code coverage effort for CR&D’s NPSE project. Research code coverage tools. Research Sugar/PSL integration and translators. Develop functional coverage modules for test bench. Coverage analysis.Design Engineer II, AST Division (2001 to 2003)Independently drive functional verification effort including test plans, test suites and test bench development. Research functional verification tools. Develop functional verification plan. Test suites. Develop ISS test bench and core processor AVP test bench. Perform regressions. Detect and track design bugs. Maintain log of findings. Interface with engineers. Present test findings to management at review meetings. Develop ISA independent and scalable IVP verification environment as Beta program with Verisity.Design Engineer II, CR&D Division (2000 to 2001)Assisted in the development of VERA test benches to verify core design. Extended test bench to verify full chip design. Developed memory access checker, trace file parser, regression scripts. Taped demo chip. Created vector test patterns for silicon testing. Developed testing to isolate bugs in silicon testing of chip. Maintained log of findings. Interfaced with engineers and colleagues from England, Italy and France.

Researched and selected software packages to establish verification environment. Developed code to perform verification algorithm of Floating Point Unit. Used ExactMath software to calculate numbers to 128 bit precision. Interfaced with Design Engineer on technical issues.KEY ACHIEVEMENTS:** Received high praise from upper management for assisting in the timely production of a working IEEE-754 Floating Point Unit architecture design for a Pentium clone chip.

Ba, Mathematics And Computer Science

Diploma

Diploma