Win Naing Email and Phone Number
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ASIC, FPGA DEVELOPMENT ENGINEERExperience in the high technology industry. Fast-paced career with industry leaders. Driven to meet or exceed project milestones. Repeatedly demonstrated ability to step into new situations and contributed quickly. Equally effective as an individual contributor as well as a team player. Highlights include:• Author Patent No.: US 10,038,632 B2Regarding Advanced Inline Aggregation (AIA) Device in Support of L2 Connected Networks.• ASIC/FPGA development experience with expertise in front end design and verification.• End to End working experiences with FPGA development from Product Requirement to Release to Production.• Solid experience in all phases of ASIC flow and have worked on module level micro architecture, design, rtl implementation, verification, gate simulation, ECO implementation and chip level design verification.• Consistently successful in taping-out five multi-million gate ASIC designs.• Packet processing/switching feature experiences.
Netscout
View- Website:
- netscout.com
- Employees:
- 2760
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Principle EngineerNetscout 2010 - PresentSan Jose, CaliforniaMicro architect, design, verify, and bring up 10G, 1G Ethernet Product by using Altera, Xilinx FPGA Device, Altera Quartus, Xilinx ISE tools for Synthesis, Place and Route and Timing Analysis and Cadence Modelsim for simulation. Packet Processing Development based on P4 Language.• Packet Processing development for different FPGA Devices and Systems.• Completed the development of NAND Flash controller and brought it up in the lab.• Maintained, Fixed Bugs and implemented the new features for current products.• Packet Processing Feature development based on Barefoot Network tofino processor using P4 Language.• Participate and write up future product development proposals. -
Hardware Engineer (2000 - 2009)Cisco May 1997 - Sep 2009San Jose, CaliforniaMicro architected, designed and implemented complex modules for five different multi-million gate ASIC chips, and one FPGA speed ranging from 167MHz to 500MHz. Supported design verification team and wrote test cases.• Conducted chip level gate simulations and found show stopper bugs avoiding costly chip re-spins. Worked with design team to fix the bugs resulting in successful chip bring up in the lab.• Performed Statistic Timing Analysis (STA, Timing closure) using IBM EinsTimer and closed timing on a couple of ASIC chips.• FPGA experience includes working with Synplicity, Xilinx ISE flow, and closed timing on Xilinx Virtex family FPGA.• Wrote test cases and tested chip/module functionality and corner cases.• Worked with Software Engineering Team During Lab Bring Up and Feature Specification.
Win Naing Skills
Frequently Asked Questions about Win Naing
What company does Win Naing work for?
Win Naing works for Netscout
What is Win Naing's role at the current company?
Win Naing's current role is ASIC/FPGA ENGINEER.
What is Win Naing's email address?
Win Naing's email address is wn****@****ail.com
What skills is Win Naing known for?
Win Naing has skills like Verilog, Fpga, Embedded Systems, Asic, Systemverilog, Rtl Design, Tcl, Functional Verification, Soc, Hardware Architecture, Pcie, Vlsi.
Who are Win Naing's colleagues?
Win Naing's colleagues are Aniket Kumar, Justin Haddad, Carl Taylor, Peter Markov, John Page, Rosa Jones, Philip Saccio.
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