Xiaobin Li Email & Phone Number

Santa Clara, California, Us

Graphics shader complex IP verifications : 1. functional verification: features include backward compatibility, instruction scheduling, pipeline hazards resolution, graphics vector ALU instruction executions.Test plan development, feature bring-up and constrained random test development and debug, own the feature coverage and pass rate closure2. shader power measurement (power virus)3. and the clock gating verification 4. shader performance verification: pipeline instruction scoreboard and scheduling performance test development and IPC-based checking

Santa Clara, California, Us

Intel SDG (Server CPU Development Group) technical lead- Led the integration SOC (full-chip ) model bring-up for multiple Xeon server CPU products- Verified the features across x86 instruction set, power and thermal management, cache coherence, etc.- Validated BIOS of DDR3 memory training sequence on the memory controller from an Xeon server CPU- Innovated a micro-architectural reset collateral for the integrated models- Developed multi-clocking simulation infrastructure- Technical leader - SoC methodology, system verilog, UVM, assertion, coverage- Random test generator