Xiaoping Ao Email & Phone Number

Over 10+ years of experience in design and implement of peripheral IPs at Freescale/Motorola.- Logic designer of MPX coherency module, and transaction target queue for MPC8640D product which has integrated Dual-Core Processor. Design features included multiple-priority arbitration schemes, address tenure streaming and data tenure streaming, out-of-order data transactions on the MPX bus, etc.- Create the SVA checker for PCI Express controller (gen1 and gen2 TLP layer). In charge generate directed and random tests, run simulations and debug design and environment issues.- Architecture, micro-architecture, and logic designer of several protocol convertors(PCIe, SATA, RapidIO, Sgmii etc). Design features included PCI Express receiver detection, symbol detecting/encoding, lane to lane alignment, PCIe training sequence control, multiple clock domain crossing, PCIe gen2 speed switch control to PHY. Debug and provide technical support for SOC and silicon bring-up etc. - Architecture, micro-architecture, and logic designer for next generation the PHY control block for advanced high speed interconnect products. It includes the PHY reset state sequence, PHY lane speed switch control block, PCIe gen3 speed switch control, etc. - Architecture, Micro-architecture, and Logic designer of FPGA bridge between Altera Arria10 and SOC.

- Logic Lead for the Eclip_EBCO external Bus ControllerDesigned and verified Eclip_EBCO core for Eclip chipset. The eEBCO provides flexible support for the attachment of SRAM, ROM, and Flash memory devices. To reduce the IO pin count, the eEBCO implements shared address and data bus up to 8 banks with dual boot address translation support. - Logic lead for the external bus controller (EBC2PLB3)Designed and implemented EBC2PLB3 core for 405 chipset. The EBC2PLB3 core transfers data between the PowerPC Local Bus(PLB) and external memory or peripheral devices attached to the external bus. The core provides support for 8 banks of the memory that may be programmed for ROM, SRAM, or external DMA device paced memory with different timing requirement. - Set up Unitsim simulation environment for ABIST engine by using TEXSIM. - Multicore simulation for the Coronado chipset. Focused on setting up the testbench which includes up to 10 plb masters and 3 pci_complex. Each pci_complex has several pci masters and pci slaves for both PCI conventional and PCIX mode. Created sag to simulate both using Verilog_XL and VCS in different variation. Debugged testcases and wrote special testcases. Created several monitors and behavior models for simulations.- Chip-level simulation for Comet chipset. Focused on setting up testbench environment including the monitors and behavior models. Developed testcases and debugged for south chipset which includes EBCO, EBMI, GPIO, I2C, UART, OPB Bridge IN, OPB Bridge OUT,OPB Arbiter, UIC, CCR.