Xiaoning Wang

Xiaoning Wang Email and Phone Number

Technical Program Manager at Apple @ Apple
cupertino, california, united states
Xiaoning Wang's Location
Dublin, California, United States, United States
Xiaoning Wang's Contact Details
About Xiaoning Wang

• Self-motivated, experienced, and independent Engineer with a strong technical expertise in Light Emitting Diodes (LEDs) and high-volume semiconductor manufacturing operations of wafer fab, packaging, metrology, electrical/optical device testing.• Strong leadership, team/project management, and communication skills through collaborations with cross-functional teams world-wide, as well as managing a team of engineering technicians, to resolve complex yield, quality, and technical challenges, from leading-edge R&D projects to fast-paced high-volume semiconductor device manufacturing.• Highly skilled in big data analysis and failure analysis for LED device performance, yield, and reliability improvements.• PhD in Mechanical Engineering with 12+ years of cleanroom/laboratory experiences in micro- and nano-scale material characterization and device design/fabrication.• Published/presented in 30+ peer-reviewed scientific journals and/or international conferences.

Xiaoning Wang's Current Company Details
Apple

Apple

View
Technical Program Manager at Apple
cupertino, california, united states
Website:
apple.com
Employees:
218112
Xiaoning Wang Work Experience Details
  • Apple
    Technical Program Manager
    Apple Jan 2020 - Present
    Cupertino, California
  • Rayvio
    Test And Reliability Engineer
    Rayvio Jun 2016 - Oct 2019
    Hayward, Ca
    • Developed automated data acquisition and analysis systems using R, Excel VBA and Access, for production line yield and reliability data analysis, as well as to drive next generation product introduction (NPI), with tightened electrical, optical, and reliability specifications while maintaining/improving production yield;• Utilized SPC and GR&R to ensure the accuracy and consistency of manual and automated electrical and optical test stations;• In charge of designing/improving testing infrastructures for various devices and form factors, to enable high-throughput wafer qualification, on-going reliability testing (ORT) of finished products from contract manufacturers (CM), as well as highly accelerated life tests (HALT). Recorded/analyzed test data for over 1/4 billion device-hours;• Developed predicative models to project LED lifetime for operating conditions from accelerated aging tests, as well as using Weibull statistical analysis and Six Sigma principles to evaluate overall product reliability with industry-leading performance;• Directed the new product qualification planning and execution during product development and launch, including temperature, humidity, ESD, vibration, power cycle, etc.;• Qualified new components and material from suppliers to ensure quality and reliability;• Performed root-cause analysis of electrical, optical, and mechanical failures from customer returns, out-of-spec parts from CM partners, as well as internal STRIFE testing failures, to strategically identify failure mechanisms and device weak points, and consequently prioritize the corresponding implementation of containment, corrective, and preventative actions to significantly reduce infant mortality rate in packaged devices by >10X;
  • Rayvio
    Chip Development Scientist / Process Engineer
    Rayvio Jun 2015 - Oct 2019
    Hayward, Ca
    • Designed and implemented modifications to production equipment to reduce precious metal consumption by >50%;• Quadrupled flip-chip SAC solderability by developing electroplated thick Ni/Au contact pad with low stress;• Developed new metal stacks for optimal ohmic contacts to both n-AlGaN and p-GaN, with superior contact quality and process stability, which resulted in a ~50% reduction in median device operating voltage by ~50%, improving wall-plug efficiency (WPE) and wear-out failure rates;• Improved equipment and process stability through design of experiments (DOE), and implementation of rigorous statistical process control (SPC) monitoring;• Successfully transitioned from chip development to highly manufacturable (DFm) 3-inch sapphire wafer LED volume production, as well as die shrinks reducing chip size by 75% while maintaining equal, or better, electrical and optical performance and lifetime. Together the yield improvements and die shrinks increased the average sellable chips per wafer by >6X;• For next generation LED chip design, developed UVC-transparent dielectric material, and UVC-reflective mirrors to maximize light extraction efficiency (LEE), quadrupling peak external quantum efficiency (EQE) of packaged devices;
  • Rayvio
    Fab Manager
    Rayvio Oct 2017 - Apr 2019
    Hayward, Ca
    • Managed up to 6 operators daily, directing workflows through front and back end of the wafer fab, coordinating with equipment engineering group on both repairs and routine maintenance, setting priorities to meet production targets, as well as helping the engineering team to achieve R&D goals;• Ensured strict adherence to all Federal, State, and RayVio environmental and safety regulations, and implemented corrective/preventative actions;• Increased annual chip production volume by >40X, and revenue by >7X, without adding new equipment or personnel;• Implemented workflows improvements throughout the wafer fab to reduce final visual yield loss by >60%, and increased wafer throughput by ~50%;• Coordinated with sales and marketing teams, as well as LED packaging CM partners to establish production schedules based on product requirements, market demands and raw material supplies, to ensure timely delivery of high-quality products;• Weekly report and update of production status, planning, and quality issues to management and engineering teams;• Drafted work instruction and SOPs for various processes-of-record and equipment, and trained operators and technicians to perform production and R&D tasks;
  • Boston University
    Postdoctoral Researcher
    Boston University Sep 2014 - Apr 2015
    Mechanical Engineering, Boston University, Boston, Ma 02215
    • Developed self-assembling techniques for large area uniform diatom (purified from live microalgae or diatomaceous earth) frustule monolayers, with nano-scale features, for dye synthesized solar cell and surface enhanced Raman spectroscopy applications.• Developed mercury vapor sensing devices based on amalgam-forming gold electrode with high sensitivity and portability.
  • Boston University
    Graduate Research Fellow
    Boston University Sep 2008 - Aug 2014
    Photonics Center, Boston University, Boston, Ma 02215
    • Characterized the mechanical properties of silicon oxy-nitride and silicon oxy-carbide thin films using nanoindentation.• Developed deposition techniques of various iron oxide thin films using DC/RF reactive sputtering;• Characterized various material properties of the iron oxide thin films using SQUID, SEM, XRD and EDX;• Designed, fabricated, and tested micro/nano iron oxide particle arrays with different structural configurations for multispectral and functional contrast agents used in magnetic resonance imaging;• Synthesized monodispersed tantalum oxide and gold nanoparticles, and developed patterning techniques forPEG-DA hydrogel particles for use in multispectral and functional computed tomography contrast agents.• Developed a simple 3-step anodization process for aluminum thin films directly grown on substrates with superior adhesion and uniformity. Achieved wafer-level uniform nanoporous AAO membrane with controllable pore size and spacing, ranging from ~90nm to 220nm;• Developed a nanomanufacturing platform based on template-assisted nanoimprint lithography using AAO membranes for cost effective and high throughput fabrication of size and shape specific polymeric nanoparticles.
  • Boston University
    Graduate Student Advisor
    Boston University 2009 - 2013
    Biomedical Engineering, Boston University, Boston, Ma 02215
    • Mentored four teams of senior undergraduate students with their final design projects in four consecutive academic years respectively;• Proposed the research topics of these projects and helped the students to understand them, and to get started with conducting their own research with literature search and planning specific aims of each project;• Guided the students through their experimental design, and trained them on all the necessary equipment/procedures,, and helped the students with the research proposal and final report writing, as well as preparing for the final presentation.
  • Boston University
    Graduate Teaching Fellow
    Boston University Sep 2008 - Jan 2010
    Mechanical Engineering, Boston University, Boston, Ma 02215
    • Teaching assistant for course ME 310 Instrumentation and Theory of Experiments, responsible for preparing and guiding junior/senior undergraduate students through different lab sessions, giving short lectures and grading lab reports on electrical, mechanical, fluidic and thermal dynamics experiments.
  • Institute Of Microelectronics, Peking University
    Undergraduate Research Assistant
    Institute Of Microelectronics, Peking University May 2007 - Jul 2008
    Peking University, Beijing, China
    • Designed and fabricated a silicon based micro-needle array for biological fluid extraction and in situ analysis, optimized the DRIE process parameters for high aspect-ratio anisotropic silicon etching;• Investigated and developed an improved structural releasing method for silicon dioxide sacrificial layers in MEMS devices using buffered oxide etchant and glycerin additive.

Xiaoning Wang Skills

Mems Matlab Comsol Microfabrication Nanotechnology Mathematica Characterization Spectroscopy Photonics Latex Powder X Ray Diffraction Labview Finite Element Analysis Numerical Simulation Sputtering Optics Microfluidics Theory Fabrication Metal Fabrication Afm Scanning Electron Microscopy Xps Xrd

Xiaoning Wang Education Details

Frequently Asked Questions about Xiaoning Wang

What company does Xiaoning Wang work for?

Xiaoning Wang works for Apple

What is Xiaoning Wang's role at the current company?

Xiaoning Wang's current role is Technical Program Manager at Apple.

What is Xiaoning Wang's email address?

Xiaoning Wang's email address is wx****@****ail.com

What is Xiaoning Wang's direct phone number?

Xiaoning Wang's direct phone number is +161741*****

What schools did Xiaoning Wang attend?

Xiaoning Wang attended Boston University, Boston University, Peking University.

What are some of Xiaoning Wang's interests?

Xiaoning Wang has interest in New Technology, Electronics, Traveling, Running, Rock Climbing And Bouldering, Piano And Music, Digital Photography, Swimming.

What skills is Xiaoning Wang known for?

Xiaoning Wang has skills like Mems, Matlab, Comsol, Microfabrication, Nanotechnology, Mathematica, Characterization, Spectroscopy, Photonics, Latex, Powder X Ray Diffraction, Labview.

Who are Xiaoning Wang's colleagues?

Xiaoning Wang's colleagues are Rhonda Copprue Goddard, Ayaan Sayed, Valeria Ruiz Alcazar, Jerry Burke, William Kannenberg, Hailing Ju, J.h Tomas.

Not the Xiaoning Wang you were looking for?

Free Chrome Extension

Find emails, phones & company data instantly

Find verified emails from LinkedIn profiles
Get direct phone numbers & mobile contacts
Access company data & employee information
Works directly on LinkedIn - no copy/paste needed
Get Chrome Extension - Free

Aero Online

Your AI prospecting assistant

Download 750 million emails and 100 million phone numbers

Access emails and phone numbers of over 750 million business users. Instantly download verified profiles using 20+ filters, including location, job title, company, function, and industry.