12+ years digital IC front-end design and flow experience. 6+ years project management experience.Experience to be a chip architect.Excellent knowledge in verilog HDL design, Cadence and Synopsys front-end tool chain.Took part in over 10 chips' tape out, play an important role in over 5 chips.Experience of complex module design for ASIC and Xilinx FPGA device.Whole front-end developing and flow experiences of digital SOC.Complex module design experience, such as cache controller, MMU/MPU, DMA etc.Low power design techniques.Deep experiences for logic synthesis, STA and formal verification with Synopsys and Cadence tools.ATE test programming, and debugging experience on Teradyne J750.Good understanding for PCIE 2.0 transaction level protocol.