Xi Zhu Email and Phone Number

A new graduate student of Electrical Engineering focusing on VLSI from University of Southern California, actively seeking full time or post-graduate intern positions of ASIC design /RTL design/ Verification starting in May 2019.2 years of academic experience in Digital design and verification. Hands on experience working with Verilog, SystemVerilog (UVM) for RTL design and verification.Tools: Design Compiler, Prime Time, Innovus, SimVision, ModelSim, Hspice, Cadence Virtuoso, Vplanner, Vmanager.Protocols: DDRx，AXISpecialties: Verilog, SystemVerilog (UVM), Python, Static Timing Analysis, Auto Place and Route, Assertions, Functional / Code Coverage.