Device Design / Technology Development Engineer
El Segundo, California
GaN FET Device Design and Technology Development (06/2005 – 12/2007):Responsible for GaN HEMT device designs. Member of Ohmic Contact Process Development Team to improve ohmic contact through design of experiments (DOE) on GaN barrier layer, Si3N4 surface passivation, contact etch, metal pre-clean, metallization, and RTA.Product Engineer / Project Manager: Design and roll out of low voltage silicon Power MOSFET (12/2007 – 09/2008); Research and development of 600V Super Junction MOSFET (10/2004 – 05/2005)Design, qualification, and rollout of mid and high voltage MOSFET (10/2003 – 10/2004)MOSFET Device Design and Technology Development:Design and qualification of 600V FET platform and fast reverse recovery body diode FET platform (05/2002 – 10/2003)Design and qualification of mid voltage MOSFET. Manages product through design, development, qualification, ramp, and volume production. The developed platform was awarded as the most profitable wafer FAB platform (10/1998 – 05/2002)Process Engineering (Rotation Program) (07/1996 – 10/1998)PVD metal thin film (Varian 3290), Wet etch process engineering (FSI); Diffusion process engineering