• Managing the “memory control and host communication component” (Store IP) of Synopsys ZeBu Debug IP stack, which includes responsibilities of: conducting system implementations, performance improvements and architectural changes in this component.• Port ZeBu Debug IP Solutions to Xilinix Versal platforms.

• Managing the “memory control and host communication component” (Store IP) of Synopsys ZeBu Debug IP stack, which includes responsibilities of: conducting system implementations, performance improvements and architectural changes in this component. • Developing high speed digital circuits for Synopsys ZeBu Debug IP solutions targeting Synopsys HW platforms.• Design and verification of firmware blocks for the power data capturing solution of ZeBu (WARHMEr) and ZeBu waveform capturing system (SaBRE).• Porting the WARHMER solution to the ZS5 Synopsys Hardware system and investigating the impact on the FPGA in terms of resource utilization and maximum speed of clocks. Optimizing and designing changes to meet the required constraints.• Managing and enhancing the existing Python Runtime Test Frameworks which is used to interactively communicate with the ZeBu HW. • Develop verification models for the ZeBu Firmware IPs using python and advanced System Verilog techniques. Carried out HW testing for Synopsys Zebu Debug IP solutions using these verification models and the runtime framework• Debugging inside the hardware using Synopsys native tools and procedures. • Synchronizing individual ZeBu Firmware IPs within a Synopsys ZeBu Debug IP solution, to ensure they function together as a system.• Debugging and fixing issues (Jiras) of Synopsys ZeBu Debug IP solutions that are found when running the full emulation flow.• Plan, guide and review the work of junior team members until completion.

• Carried out hardware and simulation verification for the overall system of ZeBu waveform capturing solution (SaBRE).• Debugged and fixed issues reported for the SaBRE. • Engaged in developing a AXI 4 protocol converter targeting towards Synopsys hardware systems. • Engaged in analyzing and debugging ZeBu Backend compile related tool failures.• Developed test plans to cover essential chip design features in HAWK tool. • Created Verilog, System Verilog, VHDL tests according to the test plan.• Developed automation scripts in python,bash,csh,tcl.• Developed a HTML based dashboard to show the quality of Hawk.• Gained experience in debugging issues with the Software and Hardware using VCS and Verdi.• Debugged inside Synopsys HW systems to analyze issues related to Hawk.

• Gained familiarity to designing Custom Processor Systems• Developed a protocol converter from AXI 4 to a custom bus protocol. • Carried out RTL Verification using UVM(Universal Verification Methodology)• Developed Regression and Perforce systems.

Conducted robotics practicals for Semesters 3 students at the Department of Electronic and Telecommunication Engineering