I have 4 years of semiconductor manufacturing experience at Micron as a process integration engineer and 3 months at Microsoft as a software engineer. I have one master's degree in chemical engineering and am now a freshman pursuing my second master's degree in electrical computer engineering.
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Technical Support Engineer微軟公司 Mar 2024 - May 2024台北AI & IoT Platform1.Debugged and tested coding in Python, REST API, and C# to analyze problems and develop solutions to meet customer requirements for getting 5 stars, involving in Azure OpenAI and Cognitive Service field2. Implemented Kusto (Azure SQL) and shell script to solve backend issues and troubleshooting problems3. Managed and well-utilized ChatGPT in OpenAI and Azure OpenAI efficiently and built modeling of LLM to find a solution as soon as possible, machine learning firmware concept -
Central Process Integration Engineer (Global)Micron Technology Jul 2021 - Sep 2022Advanced modeling software development1. Built up the modeling of the current wafer structure profile in Python language with Cadence Silvaco tool, the yield performance based on Machine Learning to predict yield performance, reduced 1 month cycle time2. Combined Photo Mask layout with coding to build memory structure profile in 150s and 140s (new series) Memory in the FEOL and MOL key loop with Linux systems3. Represented Taiwan district to transfer TCAD modeling project from the R&D site which used Synopsys system with artificial intelligence to predicate future performance, a business trip to Japan for 2 months -
Process Integration EngineerMicron Technology Sep 2018 - Jul 2021Taiwan150s, 140s, and 120s DRAM semiconductor manufacturing process development1. Improved yield and quality from 20 to 89% on Micron advanced DDR5 products with JMP, Tableau, and Y3to visualize the current wafer performance2. Rammed up yield and cooperated with process engineers, including Photo, Dry etching, Wet, CMP, Diffusion, IMP, Defect, and Metrology teams to try 30 DOEs getting high yield without Q-time alarming3. VLSI/ ASIC knowledge for Photo layout LDD and IDS P/NCH circuit from source to drain smoothly, make sure DRAM can write I/O correctly, semiconductor device background4. Suspected semiconductor failure mode via PFA and EFA, to think of weak points of the process and do optimization
Frequently Asked Questions about Yating Chang
What is Yating Chang's role at the current company?
Yating Chang's current role is UC Davis ECE master | Ex Technical support engineer @ Microsoft | Ex PIE -TCAD @ Micron.
What schools did Yating Chang attend?
Yating Chang attended 美國加州大學戴維斯分校, 國立臺北科技大學, 國立成功大學, 國立中央大學.
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