Ye Geng Email & Phone Number

Shenzhen, Guangdong, China

Responsible for the development of a series of vision algorithms for hardware acceleration (ASIC) including:- surround view for automotive and panoramic view for surveillance - ISP subsystem SOC power evaluation and power management:Develop accurate power estimation tool with CA model pre-silicon, facilitate early performance and power benchmark Support leading hw power management features and develop power management firmware to squeeze out performance &… Show more Responsible for the development of a series of vision algorithms for hardware acceleration (ASIC) including:- surround view for automotive and panoramic view for surveillance - ISP subsystem SOC power evaluation and power management:Develop accurate power estimation tool with CA model pre-silicon, facilitate early performance and power benchmark Support leading hw power management features and develop power management firmware to squeeze out performance & efficiency Show less

Glasgow, United Kingdom

Supporting the NPI & Customer engagement for the S32V Vision microprocessor, with special focus on the vision accelerators- Key contact point supporting the lead customers- Align customer requirement with internal development roadmap- Provide internal/external customer training on vision accelerators, including a series of online videos- Develop and integrate demo applications to showcase and enhance device capability

Coventry, United Kingdom

Mainly responsible for: - the testing and development of engineering prototypes in forms SW, HW and simulation - involving in the development of power modules for new products - creating electronic testing process in terms of technical details and documentation for all products - prototyping a high-speed torque sensor design carried over from university project

Sheffield, United Kingdom

Developed techniques for time stamping of data and synchronisation of a global time constant over the wireless sensor network for data alignment. The algorithm can automatically adjust the frequency at which re-sync occurs to reduce power consumption to minimum while maintaining required accuracy

Master Of Research, Integrated Photonics And Electronic System

Bachelor'S Degree, Electrical And Electronics Engineering, 1St Class Honour