Agnes Yee Email & Phone Number

Roseville, Ca

ASIC/FPGA development of storage controller SOC products, including Smart Storage Controllers, RAID Controllers, SAS/SATA IO Controllers, and SAS Expanders.

Folsom, Ca

Intel Server Emulation

Folsom, California

RTL Design Lead for memory controller for next generation SSD, using leading-edge non-volatile memory technology. Verification Lead for FPGA prototyping.• Architected design for optimum performance while maintaining compatibility with existing SSD infrastructure. • Determined optimum configuration for PHY, based on performance simulations. • Built verification environment for FPGA prototyping of next generation SSD.

Design and verification for several iSCSI, TOE and FCOE offload chips, contributing in all stages of the ASIC development cycle (From architecture to debugging failures in the Lab)• Owned design of 10G Ethernet MAC, added Ethernet Priority Flow Control and other features, integrated PHY block, corrected a lot of design flaws in the original purchased IP, provided help in testing in different levels. The design worked well in the first product, reducing time-to-market and cost significantly. • Co-owned design of Transmit/Receiver Buffer management/control block, architected and designed the high-speed/large-client memory accessing. A lot of techniques were used to reduce latency, pipelines, look-ahead, buffering, etc. The design was able to handle high traffic while saving power. • Wrote block level (UVM) and system level (System Verilog) tests to verify many functional blocks and the system. One of system level tests achived the highest bug/test ratio in the team.• Contributed in implementing Qlogic CNA/iSCSI HBA in FPGA for firmware development. This complex design was ported from ASIC and placed in Dini DVNF7A4 board. This huge 12-clock FPGA reached milestones as scheduled.

Researched, implemented, integrated, and tested new technologies/logics into print server ASIC chips. Owning ASIC developments, leading and organizing efforts in all phases of their development. • Developed the following technologies: Internet Protocol Security hardware acceleration engine, Ethernet MAC and HomePNA MAC. • Owned ASIC development for three external print server products. Organized all the design and test activities, communications with internal teams and outside vendors. One of the chips achieved production quality with a single tape-out, and task scheduling was widely leveraged in following ASIC developments.• Chosen to be Chairperson for JEDEC61 task group: JEDEC 61 task group chairperson and editor for Wireless (802.11) Upper/Lower MAC (Medium Access Control) Interface standard. Led a team of the wireless industry’s experts to develop an interface standard to enable ASIC integration of 802.11.

Design, testing and failure analysis for 2 flash memory products. Timing and functional verification of Intel chipsets and CPU.

Bachelor Of Science (Bs), Electrical Engineering And Computer Science (Eecs)

Activities and Societies: Society of Woman Engineer

General College Requirement Courses

Bs, Computer Science