Yen-Ju Lu Email & Phone Number

Lead a team on designing processor IPs.

Deputy Design Manager - 2003.3 ~ 2003.9Lead Design Engineer - 2002.8 ~ 2003.3• MIPS CPU models, simulation, and tool-chain setup• AMBA-based system bus design• Auto place & route with Cadence SoC Encounter• Lead 2 engineers

Design Section Manager - 2002.2 ~ 2002.6• Joined an ARM-based SoC project. I was responsible for ARM7TDMI integration and simulation• Trace existing graphics core’s dram controller design for reuseSenior Design Engineer - 2001.1 ~ 2002.2Design Engineer - 2000.1 ~ 2001.1• Traced Rise mP6 x86 processor design, and decoded the instruction micro-code without document• Joined an x86 SoC project and responsible for the CPU’s instruction fetch unit, branch prediction, micro-code and BIST unit• Taped out and mass produced above SoC solution (SiS 550) that comprises an x86 CPU core, north-bridge, south-bridge, and 2-D graphicsCAD Engineer - 1999.7 ~ 2000.1• Responsible for IKOS hardware accelerator cell library and macro creation, and simulation setup

• Joined an x86-compatible out-of-order superscalar processor development project. This is a multi-university project and we (NTU Archi Lab.) were responsible for branch prediction unit, reservation station, branch target buffer, re-order buffer, and completion unit. I was responsible for the branch prediction unit design

R&D Engineer - 1995.7 ~ 1997.8 (1997.1 ~ 1997.8 part time)• Developed programming drivers for programmable devices such as micro-controller, FPGA, CPLD, Flash, EPROM, etc.

M.S., Computer Science

Master, Finance

B.S., Electronic Engineering

A.E., Mechanical Engineering