Yi Ming Tseng Email and Phone Number

Synopsys:September 1999 ~ July 2024 : over 24 years.Professional Service Group from September 1999 to February 2002, In charge of IC design methodology development and flow deployment, created RTL-QA environment for RTL coding qualification and lint, Synthesis for low power, DFT (Design For Test) and STA (Static Timing Analysis) sign-off. Familiar with TCL / TK, Perl, Make and gcc EDA related development environment. Supported GSM related project services for MediaTekSenior Staff Application Consultant (AC) from February 2002 ~ July 2024, The first 2 years in AC, he was placed in charge of Electronic system level (ESL) design and verification using Synopsys COSSAP, System Studio, VCS, and SystemC Compiler behavior synthesis tools supporting. The 3rd year and up to now, he is placed in charge of Synopsys synthesis tools, large chip hierarchical design flow, high performance and low power design flow for CPU and GPU, and multi-voltage UPF design flow, STA sign-off flow and DFT flow, of cause understand the RTL to GDSII, and Physical design flow. Yi-Ming has many experiences to co-work with many global account companies to finish chip tape out.

March 1994 ~ September 1999 : about 5 years  An application engineer of DSP group, response for DSP ICE (In-circuit emulation) development, FPGA board development, and L&H speech-compression algorithm importing for answer machine. In charge of Holtek microcontroller testing.  An IC designer, in charge of Pager microcontroller SOC chip design.Familiar with BCH error correction algorithm and decoder IC developmentIntegrated the Holtek 8-bits microcontroller and pager decoder circuits together Developed Holtek Pager chip IC specific, and investigated Pager chip market, played as an IC specific planner.

 Worked for TSMC as an engineer.