Yi-Ting Wu Email and Phone Number

Expertise:1. Transistor characterization and process integration2. SRAM and emerging memory development (process, layout, characterization)3. Device modeling (BSIM) and analog circuit designs4. Chip yield enhancement, CP testing, reliability, and mismatch5. TCAD simulation / emulationSkills and Abilities:1. 10 years in the R&D device division of the third largest foundry (UMC): 1-1. 28, 22, and 14nm nodes: transistor characterization, layout, and modeling 1-2. STT-MRAM: bitcell design, layout, characterization, and yield analysis 1-3. Familiar with FinFET, planar CMOS, and STT-MRAM processes 1-4. Intensively work with process integration teams and product (yield) teams 1-5. Good coding skills to effectively analyze data (Excel VBA and Python) 1-6. Rich experiences in Taguchi design of experience (DOE) 1-7. Rich experiences in chip yield analysis and enhancement (CP testing) 1-8. Familiar with the analog circuit design (e.g., bandgap reference circuit)2. 7 years in TCAD / circuit simulation: 2-1. Synopsys Sentaurus / Coventor SEMulator3D 2-2. HSPICE and Verilog-A (transistor modeling) 2-3. SRAM simulations, modeling, and yield projection3. Hold a habit of annually studying textbooks and IEDM/VLSI-T short courses related to device physics, semiconductor process, analog / memory circuit designs, and spintronic physics.4. Enthusiast, ambitions, and innovation: pursue to be a technological leader instead of a follower, always try to find a smarter way to make products better.5. Teamwork: love to constructively discuss with people without hiding.Honors1. 18 IEEE journal paper publications and nine patents holding.2. Hold three critical patents which increase the yield of STT-MRAM.3. Obtaining the Ph.D. degree by exchanging to U.C. Berkeley for two years and publishing 5 IEEE transactions there (4 of them are first author paper), fully funded by Taiwan Government.