Yiting Lin Email & Phone Number

• Testing engineer in AMT company now, focus on test and verify of the phase memory, includes programming the Verilog HDL in Cadence, and uses the NCSIM to figure out the solution to settle problems during design period. • Master graduated from the Engineering Business Management of University of Sussex in 2015, for accounting and finance industry has a solid foundation of knowledge; unique insight to management; proficient in marketing planning; Interesting in Robotics intelligent control.• Bachelor graduated from the University of Central Lancashire in Electronic Design Automation (EDA) in 2014; proficient in a variety of software and programming languages; familiar with object-oriented programming. • Fluent spoken English; Native Cantonese and Mandarin Chinese• Exceptionally motivated and able to motivate others; a self-starter.• Exemplary interpersonal skills and organizational skills.• Equally effective researching independently and as a dynamic team member.• Fast learner who can quickly grasp and apply new ideas.• Excellent communication skills and spare no effect to show friendly to customers.

Listed skills include C++, C, Teamwork, Powerpoint, and 21 others.