Yoichi Uchida Email & Phone Number

1. Hardware design of a processor in the interface to the RF chip and verification for WCDMA modem supporting HSPA2. Hardware design of a processor in WDCDMA modem featured HSPA which controls the interface part to the RF ASIC and verification3. Hardware design of a processor in RF ASIC which is a counter part of the WCDMA modem chip featured HSPA and the verification of the deisgn4. Hardware design of Synchronization Chanel Canceller implemented in the WCDMA modem chip… Show more 1. Hardware design of a processor in the interface to the RF chip and verification for WCDMA modem supporting HSPA2. Hardware design of a processor in WDCDMA modem featured HSPA which controls the interface part to the RF ASIC and verification3. Hardware design of a processor in RF ASIC which is a counter part of the WCDMA modem chip featured HSPA and the verification of the deisgn4. Hardware design of Synchronization Chanel Canceller implemented in the WCDMA modem chip working with LTE chip5. Verification of the SCH Canceller with System Verilog6. Enhancement of the processor in the RF ASIC to improve the data transfer performance and its verification.7. Hardware verification of Rake and Correlation matrix generator referring to the result of the Rake using Specman Show less

1. Design support for customers talking to them face to face to suggest the best solution2. Implementation of the DFT including from synthesis, scan insertion, timing analysis throughout layout support.

Giving design support to customers as a chip vendorPresenting strategy for the chip delivery meeting customer's expectationGiving solution to problems about area, timing and testabilityOptimization of customers' designTiming analysis, DFT insertion and interfacing to layoutEricsson Japan * * Jan 2006- *Design and verification of a processor interfacing to RF ASIC in WCDMA modem supporting HSPATaking a responsibility for maintaining a series of the… Show more Giving design support to customers as a chip vendorPresenting strategy for the chip delivery meeting customer's expectationGiving solution to problems about area, timing and testabilityOptimization of customers' designTiming analysis, DFT insertion and interfacing to layoutEricsson Japan * * Jan 2006- *Design and verification of a processor interfacing to RF ASIC in WCDMA modem supporting HSPATaking a responsibility for maintaining a series of the processor mentioned above for some projectsVerification and supporting design of Synchronization Channel Canceller block in a WCDMA modem chip working with LTEVerification of Rake and Combiner block in a WCDMA modem chip Show less

1. Audio CODEC hardware development2. Signal processing of each broadcasting formula of TV3. Was in charge of L3, I2C bus IPs and interpolation filter hardware development

Development of audio codecTaking a responsibility for top integration of a chip processing a signal on TVDesign of interpolation filter which includes DSPDesign of I2C and L3 block for audio codec

1. Hardware development of DSP in a chip for exchanging machine2. Working on interpolation and decimation filter hardware development3. Debugging our products and gave on site suppurt to NTT which was our customer

Development of DSP in a IC chip for exchanging machine for NTTSupporting design and verification of interpolation and decimation filterOn site debug and support of the product at NTT office

Bachelor, Electronics

B.A, Electronics