1. top level rtl-mbist2. top level synthesis3. top level CBDFT4. top level ATPG ENV maintain and pattern generation5. ATE test, SAF pattern failure diagnosis and pattern mask.6. IDDQ pattern generation, ATE test, and current analysis.

1. Setup and maintain synthesis FLOW, dc_setup.tcl and library.2. Do synthesis with different solutions for better timing and area.3. Do formality verification check based on Conformal tool.4. Setup and maintain RTL-MBIST FLOW based on tessent tool, work on top-level and block level RTL-MBIST insertion, and Rtl-MBIST simulation with VCS tool.5. work on SCAN insertion based on test-kompressor/DFTcompiler tool and non-scan analysis.6. work on ATPG and do coverage analysis for coverage improvement.7. Do patttern simulation based on VCS tool.8. whole chip TEST mode timing constraint owner, make sure high quality test mode timing constraint.9. whole chip TEST mode STA, timing analysis and fix, including clock tree tune, insert delay cell , analyze timing path in physical view by Tweaker tool and work with PD owner make sure timing ECO are as expected.

1.adept at Scan insertion ，ATPG，and simulation in both tile level and SOC level .2.good at Mentor DFT tools.3.have ATE pattern diagnosis experience.4.skilled in Shell，perl ，and TCl.