Yu-Cheng Chiu Email and Phone Number

* Adept ASIC design engineer with 10 years of experience and successfully delivered ASIC projects * Worked in several areas of ASIC design that include top-level integration, micro-architecture specification, RTL development, synthesis, static timing analysis (STA), validation, debug, and chip characterization * Self-motivated with ability to work independently and interact interdisciplinary with engineers across teams* Collaborated effectively with verification team on test plan, coverage plan, and coverage closure * Knowledge of clock domain crossing (CDC), power domains, and low-power design techniques* Experienced in developing and supporting a fully automated flows using Perl, Tcl, and Shell scripts* Possessed strong technical, debugging, and problem-solving skills in RTL and gate-level simulation * In-depth knowledge of both front-end and back-end ASIC design methodologies