Yufeng Luo Email & Phone Number

San Jose, Ca, Us

San Jose, California, Us

I lead the Digital Design Implementation (DDI) Business Unit, the R&D organization of Genus (synthesis), Innovus (physical design) and Joules (RTL power). Meanwhile I continue to be a major technical contributor, especially for new technology development.

San Jose, California, Us

I managed the IC Digital (ICD) Business Unit, the R&D organization of Innovus, Cadence's physical design product.

San Jose, California, Us

I led the team, as the main architect and manager, to design and develop GigaPlace - the next generation placement engine in the Innovus physical design product.

Wilsonville, Or, Us

After joining Mentor Graphics with the Sierra acquisition, I managed the core optimization team while continued to be the main technical contributor. Assembled the team from scratch, recruited and trained the new team members. The team has been consistently delivering runtime and QoR improvements every release.

Us

I was one of the earliest members in this start-up company. Technical lead of the optimization team. Invented, architected and implemented the optimization algorithm based on bottleneck analysis and analytical optimization (US patent 7,191,417). Invented and implemented the “predictive timing” algorithm for circuit performance prediction, which enabled innovative algorithms in timing driven placement, floor-planning, timing constraint debugging, etc.I also designed and implemented the multi-threading infrastructure, designed the multi-threaded timing analysis algorithm, and helped the timing analysis team on the implementation of this algorithm.Company successfully acquired by Mentor Graphics Corporation in June 2007.

Sunnyvale, California, Us

I was one of the earliest members in the Physical Compiler group. Technical lead for the timing optimization team. Contributed to a wide range of aspects of the product additionally, including virtual route, timing driven placement, and even a Java based GUI for design visualization during debugging.I also led the team to re-implement the infrastructure (“XG mode”) for better capacity and runtime. Designed the overall architecture and led the implementation of the new physical data model. Promoted good software engineering practices to improve product quality.After the Avant! merger, I was member of the expert team to define the combined Physical Compiler and Astro technology, which later evolved into IC Compiler. I designed and prototyped direct integration of Synopsys physical synthesis data model with the Avant! Milkyway database.Recipient of the 2002 corporate “Excellence Award”.

Wrote a SPARC-V9 assembler using C++ to support the design of a 64-bit Ultra-SPARC compatible microprocessor (Viper).

Participated in the development of a data migration and cleansing software. Wrote TCP/IP based distributed programs in C++. Company later successfully acquired by Compuware Corporation.

Ms, Electrical And Computer Engineering

Graduate Student (Transferred To Ut-Austin), Computer Science

Bs, Information And Control Engineering