High performance memory to IoT and on-device AI.

Responsible for STT-MRAM product definition, design execution, and market development.

Lead STTMRAM technologist - first fully functional 40nm embedded MRAM macro that measured <1/100 of typical FLASH programming energy, process integration lead; IMEC and foundry interface; project and test-chip coordination; 19 filed patents under two years and PRB chair

22nm SOI CMOS technology gate patterning module integration owner – plan and execute process improvements on gate etch profile, CD uniformity, defect reduction, and device performance. I lead the module team to achieve significant improvement in gate profile over a short period of time, in parallel with process design and installation. Working through systematic defect sources, defect density level was reduced by more than factor of twenty. 22nm SOI CMOS technology process assumption –technology process assumption document was setup for model development and inter-module coordination. Key challenges and their interactions were identified for resource prioritization. Process assumption documentation was also used to smooth testsite transition and achieve first-time right on early user hardware.Design and setup short-loop process flows to support sister teams for MOL, BEOL, and 3D integration development. Collaborate with process emulator vendor to develop tool capability.

Chief scientist for developing the Magnetic-Random-Access-Memory (MRAM) as a replacement for on-chip L2 cache, and developing the racetrack memory to supersede FLASH. Job responsibilities include (1) MRAM and racetrack memory integration, (2) test site design and coordination, (3) functional and parametric test development, (4) MRAM design manual and magnetic device specification author and owner, and (5) magnetic cell design task force leader.Major achievements include: (1) Accelerated development cycle by a factor of 3 by inventing a “short-loop” design and process. (2) Improved device yield from 99% to 99.99% by identifying and resolving critical yield detractors. (3) Increased productivity by creating a suite of MatLab routines for data analysis and presentation. (4) Identified the write current as the main limiter for MRAM scaling at an early stage. This helped the whole project to refocus its activities, and is by now a fact well recognized by all MRAM groups. (5) Improved communication by acting as the repository of MRAM and semiconductor related knowledge and ideas, and the interface between multiple divisions within IBM.

MTJ-MRAM device physics study and process development.Design and setup of semi-automatic general purpose test stations.