Logic design engineer as part of the PLL team in Intel Jerusalem. Owner of PLL design.• Design and implementation of digital controllers for PLL control circuits. Complete responsibility over the digital micro-partition including:- Working in unison with analog designers on the PLL’s design. Integrating between the analog and digital partitions.- Full responsibility of digital code implementation, from the specifications to the final code.- Working with customers and debugging the product in their local environment.- Providing specifications, constraints and support for synthesis flow.- Defining the test plan and running validation of the design, both at the sub-block level and top level.

Intern in the DA (design automation) team in Intel Jerusalem.• Software and Hardware validation tool development.