Yuval Gilad Email & Phone Number
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Yuval Gilad is listed as A good engineer based in Austin, Texas Metropolitan Area, United States. AeroLeads shows a matched LinkedIn profile for Yuval Gilad.
Yuval Gilad previously worked as Applications Engineer at Tenstorrent and Staff Applications Engineer at Arteris Ip. Yuval Gilad holds Master'S Degree, Electrical And Electronics Engineering from Tel Aviv University.
About Yuval Gilad
Experienced solutions and applications engineer, responsible for direct and consistent business success with the products that I was involved with.Design Verification skills : UVM (SV,e,ML) , RTL (Verilog , VHDL), functional verification debug best practices and methodologies , Cadence tool flowsSoftware skills: Scripting languages (Python, Shell, Perl), AGILE development and product ownership, Linux/UnixBusiness development skills : pre-sales/post-sales content generation and delivery , strategic roadmap planning, customer engagement campaign planning/execution, customer engagement and customer training creation and delivery
Yuval Gilad work experience
A career timeline built from the work history available for this profile.
Staff Applications Engineer
- provide guidance , consultation and support on network on chip (NoC) construction and analysis to match the client's area+performance requirements- Build Network on chip systems according to client's area/performance specification- provide training on Arteris IP products- Provide collateral tools and python scripts to overcome missing functionality in the tool - create and consult on creation of training material- Expertise in AMBA protocols- Debug of complex customer Interconnect issues- Take part in product specification , development and validation
Principal Application Engineer
- Technical support for the Cadence frontend simulation solutions suite - consult existing customers on best practices, methodology and usage of the Cadence simulation tool suite to maximize efficiency and value to the customer- help plan and execute product proliferation to increase usage of purchased products and consider how other products could be used to provide more value and increase revenue at the same time- create plug ins and complimentary tools tailored to specific customer needs, building on top of the different Cadence tool extensions (Python APIs, TCL, etc...)- prepare, and present pre-sales content to potential customers
Sr Principal Solutions Engineer - Functional Verification Tools
Acting as the main point of contact for SoC design and verification debug solutions and methodologies in Cadence Design Systems , North AmericaAchievements1. created and delivered pre-sales content that contributed to business wins2. providing quick support to customer to increase overall satisfaction3. guide customers on debug methodology to improve overall debug efficiency4. continue working with customers to proliferate usage to other teams and increase revenue5. automated process to improve tool qualitymy roles and responsibilities are:1. work with customers to gather requirements for the development of best in class functional verification debug tools. write solution spec and work with graphical designers to generate graphical spec to be approved by internal reviewers and customers2. work with R&D and manage AGILE sprint planning to hit roadmap deliverables3. create , maintain and deliver pre-sales overview and training material to application engineers and customers on our functional verification debug solutions4. develop debug methodologies and consult customers on best practices for RTL (Verilog/SV/VHDL) as well as HVL (specman e / UVM SV) debug to reduce overall time to fix bugs 5. develop novel internal tools to generate complex design and verification environments using scripting languages (Python , tcsh ,etc..) to stress test our debug solutions6. work with sales and technical field engineers to identify potential customers to engage with, as well develop strategies to maximize proliferation and revenue7. work with solution engineers from other teams to find develop tightly integrated user flows for ease of use
Hw Engineer
1. PCB Analog design2. research various paralleled power supply challenges and solutions (DROOP, load sharing ,coupled inductors etc...) and simulate and design various solutions.3. Magnetic components design.3. Lab testing of various portions of our PCBs using lab equipment.
Lead Product Engineer - Verification Ip Group
In this position I supported Cadence's AMBA protocol family customers, and helped them successfully integrate Cadence's AMBA verification IP's within their verification environments.This role requires expertise in the AMBA protocol family, UVM, System Verilog and Specman.In this position I took upon the following tasks:- Expert on AMBA AXI/ACE protocols.- Provide methodological guidelines on how to use our verification IP in the most efficient manner memory-wise and CPU time-wise- troubleshoot/modify the Customer's scripts to embed our products correctly in their flow.- Support customers and help them solve testbench or DUT issues.-report bugs in the Verification IP to R&D and suggest possible fixes.- Provide functional code solutions and workarounds for customer enhancement requests.- Write complimentary documentation, solutions and articles.
Application Engineer
Working in the Cadence Design Systems Israel R&D center (formerly Verisity) as part of a global support team specializing in the verification solutions.My responsibilities are to provide the highest standard of Tier 1 and 3 support in the following fields: 1. Specman and the e language / UVM e. 2. SystemVerilog / UVM SystemVerilog 3. UVM multi language verification solutions ( SV-e, SC-e , etc..) 4,Incisive Debug Analyzerthe support i provide includes: 1. debug tool errors, crashes, memory issues and unexpected behavior for the above products. 2. methodological consulting (mostly for UVM e/System Verilog). 3. Deliver frontal training: Specman basic training / Debug Analyzer workshops. 4. provide e/SystemVerilog code segments and solutions tailored to customer requirements. 5. take an active part in the Stackoverflow.com's Specman community.(as a supporter/Teacher). 6.writing support and methodology articles to be added to internal and external support database. 7. on site customer support - solving customer issues and integrating our products into user environments on site.i am also responsible for my team's tools,utilities and scripts, which i have implemented in Perl and Shell script.
Vlsi Design And Verification Engineer
In this position, i took part in the design and verification team of one of the company's medium scale communication Chip.my responsibilities were: 1. block level HDL design (Verilog) 2.writing test plans and implementing with specman ( e language) 3.debugging and solving Clock Domain Crossing issues. 4.writing technical specs for the Block i owned..
Mobile Applications Developer
recieved the company's customers specifications and designed Java ME Mobile applications for them.
Private Tutor
taught undergrad students, material they've been having problems with in several courses from the engineering department. such as:-Introduction to computer architecture-Introduction to semiconductor.-Semiconductor components and applications
Yuval Gilad education
Master'S Degree, Electrical And Electronics Engineering
Bachelor Of Science (B.Sc.)`, Electrical And Electronics Engineering
Frequently asked questions about Yuval Gilad
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What is Yuval Gilad's role at their current company?
Yuval Gilad is listed as A good engineer.
Where is Yuval Gilad based?
Yuval Gilad is based in Austin, Texas Metropolitan Area, United States.
What companies has Yuval Gilad worked for?
Yuval Gilad has worked for Tenstorrent, Arteris Ip, Cadence Design Systems, Solaredge Technologies, and Pmc-Sierra.
How can I contact Yuval Gilad?
You can use AeroLeads to view verified contact signals for Yuval Gilad, including work email, phone, and LinkedIn data when available.
What schools did Yuval Gilad attend?
Yuval Gilad holds Master'S Degree, Electrical And Electronics Engineering from Tel Aviv University.
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