• As the leader of company’s National Project office, in charge of setting project plan, application, contact window to outside and coordination of project progress, etc. to ensure the whole development schedule as planed;• Being in charge of the company’s IP work, setting up the data source, analyzing the IP risk, improving the IP management system, managing the daily IP affairs.

• Starting from almost zero, independently, in charge of setting up Huali’s Technology Development Division to include FEOL PIE, Device, BEOL, YE, Spice, TCAD, testing, layout, Photo, Etch, DCVD, PCVD, IMP/Diff, CMP/ECP, WET, etc. functions;• As Deputy Division Director, manage the whole division and make it work smoothly;• As the leader of one batch of transfer team, ensure the smooth technical transfer and manage the whole team;• As the vice chairman of company IP Committee, set up IP system for company, manage and ensure to meet every year’s company target.

• As BE manager, in charge of foundry based 40nm Cu/low-k back end of line (BEOL) process integration, reliability and yield improvement;• Set up foundry based all BE process for customized approach;• Customer new tape out;• Process/reliability issue debug to meet customer’s requirements;• Routine management works.

• Work closely with individual module to monitor inline lots’ movement to resolve line issues or to ensure that there are no process issues with production lots;• Resolve all process integration issues by ensuring all window checks are done on critical process steps;• Being the only contact window from Fab, work closely with Customer Engineering (CE) and Sales to resolve customer complaints and provide customers with required information;• Maintain good Cpk for ET and monitor inline SPC parameters for assigned process;• Identify and correct all ET related problems that may affect seamless production;• Perform low yield analysis and issue debug for yield improvement.• Routine management works.

• Process integration and yield improvement for 90nm technology node;• Reliability improvement; • Coordinate technical transfer from TD to Fab.

0.13 m Cu/low-k (SiLKTM, Dow Chemical Co.) and Cu/ultra low-k materials (p-SiLKTM of Dow Chemical Co., NanoglassTM E, of Honeywell Electronic Materials) (both CVD and spin-on types) process integration and yield improvement • Extensive work to choose a suitable integration scheme, capping layer, and hard mask for Cu/low-k and Cu/ultra low-k processes• In association with module development engineers to optimize the module process recipe including dielectric deposition, lithography, etch, clean, barrier layer deposition, Cu metallization, planarization, and so on • Process in-line design rule check and control and defect control• Electrical testing and data analysis

• In-charge of the backside processing for the fabrication of III-V semiconductor monolithic microwave integrated circuits (MMICs) that includes wafer mounting, bonding, lapping, polishing, via hole etching and metallization• Via-hole etching process development for III-V semiconductors by both reactive ion etching (RIE) and electron cyclotron resonance (ECR) etching techniques using different plasma chemistries• Development of a reliable and repeatable wafer backside process and application to MMICs• Device fabrication experience for sub- PHMET devices

• Project leader, National Eighth-Five-Year Plan (1991-1995) Development of a new Ti-alloy for cold-rolled sheet for use as a structural part in aircrafts This project was awarded the Best Project from China Air Force in 1996• Project leader, National Ninth-Five-Year Plan (1996-2000) Development of Ultra-High-Strength Ti-Alloys Coordinating several activities (including five companies and two research institutes) on the design and development a new Ti-alloy structural part with higher strength and lower weight for aircrafts