Pre-silicon Verification Methodology:- UVM methodolgy for reusable verification components- Automatic testbench building- Verification IP flows & guidelines handling- Mixed-signal SOC verification flows (AMS/DMS)- Verification trainings: - Formal verification sign off flow (Jasper) - Portable Stimulus Standard (PSS) - Verification IPs design toward reusabilityR&D Efficiency:- Common-Building-Blocks (CBB) setup- Bug tracking platform building & flow setup- GUI-window-push tool- Chatgpt based AI-helperBattery Management:- Verification strategy definition, plan setup- Digital testbench design, VIP design- Mixed-signal testbench design (test cases definition, checkers, integration of digital & analog models)- Gate level simulation, power simulation flow setup- Pre-silicon verification quality tracking (coverage, requirements, regressions etc.)- Post-silicon debug support for lab verificationElectronic gauge:- Block-level testbench design & verification- Synopsys VIPs integration- Reusable block level testbench design- System-level testbench design & functional verification- UPF flow setup- Mixed-signal verification- Debug support for FPGA prototype verification

- Block-level verification plan setup & testbench design & verification- Mixed-signal simulation of MCU

- As volunteer of "Green River", protecting bar-headed geese, installing wildlife monitoring equipment, receiving tourists, and picking up garbage, during three-month stay in Hoh Xil, the source of the Yangtze River, Qinghai, China.- Participated in the "Positive Psychology Instructor Training Class" held by the School of Social Sciences of Tsinghua University, and passed the assessment.- A lot of reading, including psychology, philosophy, famous novels, efficiency improvement, etc.- Self-practice of "We Media", including writing, making videos, etc.

- SOC IPs verification of wireless baseband (in-chip debugging block CVC STM, inter-chip block ESPI, etc)- Requirements learning, test plan setup, testbench building, testcase setup, coverage analysis, etc- Testcase regression & debug- Debug support for System/FPGA-level verification

- Integrated the NVIDIA Deep Learning Accelerator(NVDLA) into the IBM OpenCAPI framework.- Analyzed the different configurations of NVDLA and its resource utilization on the FPGA.- Data protocol conversion and IP integration.

- Design and debug FPGA logic for aerospace projects- Functional test of the product- Write and maintain the project documents