• Led microprocessor DFT structural testing using Scan methodologies across all aspects of product design: driving technology readiness, micro-architecture, logic and physical design, automatic test pattern generation (ATPG), pre and post silicon debug and fault grading. • Technical consulting to company manufacturing engineers in area of silicon defect failure and root cause analysis. Organized and drove technical meetings and best-of-known methods across variety of microprocessor and chipsets teams. Used various internal/external software tools based on logic and layout design to quickly root cause defects in sort wafers, class units or customer return parts. Key contributions:● Facilitated DFT RTL scan feature implementation: DFT logic/control signals coding and validation, managed DFT global clock implementation● Defined scan chain partitions, insertions and routing for physical implementation; validated statical timing analysis; led netlist validation● Defined pre/post silicon ATPG tools and flow; performed ATPG pattern generation and validation; led ATPG silicon debug● Computer-aided design development and debugging for logical and silicon based failure analysis

• Developed and implemented new Design for Test methodology for defect diagnosis targeting bridge defects by processing full chip layout design and extracting realistic bridge faults based on given defect size. • Designed CAD EDA tool, Computer-Aided Fault to Defect Mapping (CAFDM), based on new methodology predicting layer and coordinates of possible chip defect(s) providing precision and running time advantage over current commercially available tools.• Participated in International SEMATECH meetings related to proliferating new CAFDM methodology to representing member companies; reported quarterly progress and using feedback for further project focus.

CAD engineer