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Zubin Patel is listed as Technical leadership spanning | Quality | Reliability | Failure Analysis | Image Sensor |Statistical Data Analysis | materials and characterization | resourceful | critical thinking at OMNIVISION, based in San Jose, California, United States. AeroLeads shows a work email signal at onsemi.com and a matched LinkedIn profile for Zubin Patel.
Zubin Patel previously worked as Quality and Reliability at Omnivision and Principal Engineer Failure Analysis/Computer Integrated Manufacturing (Intelligent Sensing Group) at On Semiconductor. Zubin Patel holds Ph.D, Physics/Material Science from University At Albany.
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Quality, Reliability, Failure AnalysisCross Functional Technical leadership with proven deliverables and results.Professional with experience and knowledge in System Level Debug, Device Physics, Material Science and Process Technology.Development and optimization of thin films using CVD, PVD, ALD and Epi (a-Si, Si, SiGe and Ge).Process Development: Annealing /Oxidation /Doping Furnaces, Wet Benches, Lithography (ASML PAS 5500/60) and Etch Characterization of materials using RBS, NRA, XRD, HR-XRD, SEM, AES, XPS and Spectroscopic EllipsometryDevice characterization, Bench Characterization and Analysis of Parametric Data.Well versed in Modeling of Semiconductor Devices and BEOL parasitics using Circuit Simulators, Device Simulators and Process Simulators; HSPICE, TSUPREM4, MEDICI, RAPHAEL, BSIMProPlus.Programming languages (GNIIT)6 Patents (4 granted)9 PublicationsSpecialties: Semiconductor device characterization and modeling. DOE/ Data Mining, Analysis, Presentation New Product Validation/ Qualification Interconnect modeling, wire models and physical design development support. Growth and characterization of thin films. Process development and optimization. Excellent communication and interpersonal skills. Self-motivated, self-directed and a team player. Demonstrated ability to work effectively across cross- functional teams. Customer communication. Technical Writing Flexibility and adaptability to accept new tasks Dynamic and “can do” attitude with the desire to work with a great team and product HW/SW/FW debug and analysis High attention to detail, thirst for knowledge, and an inherent interest in solving engineering concerns
Listed skills include Characterization, Thin Films, Semiconductors, Cmos, and 26 others.
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Santa Clara, Ca, Us
Improving Quality and Reliability of products by raising the bar for failure analysis while also improving KPI's.Known in the company to visualize trends much before being confirmed and addressed.
Scottsdale, Arizona, Us
Bridging the gap(s) between failure analysis, production engineering, application engineering, design, wafer processing, package, and assembly process and reliability.
Scottsdale, Arizona, Us
Perform electrical analysis including fault isolation, curve trace diagnostics and physical failure analysis using both conventional and advanced backside analytical instruments and techniques.Experience and demonstrated technical expertise in physical failure analysis based on parametric data, ATPG diagnostics and BIST isolation.Functional knowledge of transistor device physics, advanced CMOS manufacturing processes, circuit analysis, advanced surface analysis analytical techniques. Mentor less experienced analysts and participate in advanced tool related characterization.Provide feedback and support to PE/ TE/ DE based on lesson learned.
San Jose, California, Us
Responsible for driving 8D response and corrective actions to customer for automotive as well as mobile products.Electrical Failure Analysis and Physical Failure Analysis on CMOS image sensor components.Electrical Validation and Characterization. Bench Probe and system level EFAAbility to complete test and resolve problems in unattended manner. Synthesizing root cause and recommended corrective action from the results of multiple analytical data sourcesImplementation of corrective actions maintaining a close loop with wafer-FAB and assembly sub-contractors.
Initiated and led the front end of solar cell development from a concept in a small lab to prototypes at SNF. Key contributor in the development of HIT (Hetrojunction with Intrinsic Thin layer) solar cell which provided efficiency in higher double digits. Lead in process development and optimization SiGe based solar cells.
Materials research and engineering and process development and integration using Stanford Nanofabrication Facility.Leading the development for- Multi-layer reflective stack which provided excellent match between measured and simulated data for reflectivity.- Anti-reflective coating (ARC).- Metallization schemes. - Method of emitter formation- Electrical testing IV, EQE and CV measurements in determining active dopant profile in the intrinsic layer and junction characterization.- Created process guidelines based on PC1D modeling- Texturing of silicon for light trapping. - Device and material development using various characterization from ellipsometry for thickness, n and k measurements, RBS, XPS and SIMS for compositional analysis and depth profile, AFM for surface roughness, XRD and HR-XRD to determine phase composition, lattice parameters, crystal structure, epitaxy and orientation.
High k development using Stanford Nanofabrication Facility- Development and integration of high dielectric constant material for device applications.- Process development and verification using CMOS process flow. - Hands-on experience with various deposition tools (CVD and PVD), oxidation/annealing furnaces, etch tools, optical lithography and wet benches.- Hands-on experience with various characterization tool including SEM, Prometrix and Ellipsometers- Bench measurements and electrical characterization including CV, IV and stress measurements.
- Pixel Development and Optimization using TCAD simulations and Device Characterization.- Developed Models for Periphery Devices. - Developed and supported selected sections for Electrical Design Rule & Technology Design Rule- Lead a team in charge of packaging devices for optical characterization based on parametric data.- Interfacing foundry to transfer process development and monitor critical process parameters.
Sunnyvale, Ca, Us
- Developed Models for Periphery Devices, Core Devices and Back End of Line Parasitics.- Device characterization and parameter extraction- Developed and supported selected sections for Electrical Design Rule & Geometric Design Rule- Provided an active Technology interface between Process Development, Design and CAD groups- Provided designers with parasitic predictions and Models at preliminary stages of new technology nodes- Developed, implemented and supported HSPICE Wire Models for Modeling Interconnects across all existing technologies - Developed a first pass parasitic alert system for full chip extraction data.- Development of test structures required for Modeling Interconnects.
Growth and characterization of high dielectric constant materials for nanoscale device applications
Development of Oxide Growth by Chemical Vapor Deposition (CVD) using Liquid Delivery Source
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Zubin Patel works for OMNIVISION.
Zubin Patel is listed as Technical leadership spanning | Quality | Reliability | Failure Analysis | Image Sensor |Statistical Data Analysis | materials and characterization | resourceful | critical thinking at OMNIVISION.
AeroLeads has found 1 work email signal at @onsemi.com for Zubin Patel at OMNIVISION.
Zubin Patel is based in San Jose, California, United States while working with OMNIVISION.
Zubin Patel has worked for Omnivision, On Semiconductor, Aptina, Silexos, and Ubimos.
You can use AeroLeads to view verified contact signals for Zubin Patel at OMNIVISION, including work email, phone, and LinkedIn data when available.
Zubin Patel holds Ph.D, Physics/Material Science from University At Albany.
Zubin Patel is listed with skills including Characterization, Thin Films, Semiconductors, Cmos, Failure Analysis, Silicon, Cvd, and Device Characterization.
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