802.11o Detection of packet and its type: Improvement of existing algorithm and implementation of C++ reference model. Design of performance metrics and its integration into C++ reference model. Performance measurement and analysis. Leading of C++ reference model and HW implementation alignment.o Channel estimation: Development and implementation in C++ reference model.o MU/SU beamforming: Improvement of existing algorithms. Support of new approach integration in HW. Leading of C++ reference model and HW implementation alignment.

Development of physical layer algorithms and software for LTE Cat-M1 modemo Secondary Synchronization Signal (SSS) detection block: development of C++ reference model and corresponding C driver code for ARM processor. Verification test plan design and test vectors generation.o Reference channel estimation: algorithm development and implementation of reference channel estimation. Integration into system level simulator and real channel estimator performance measurement.o Performance testing using LTE Cat-M1 system simulator for system performance, algorithms (initial cell search, channel adaptation, channel estimation) verification and improvement. Implementation of performance test simulations including post simulation results analysis using python.o PBCH processing: development of driver code to support PBCH repetitions

3GPP LTE (2013-2015)- Familiarization with LTE standard. Studding of the PHY Layer functionality and requirements for Uplink/Downlink FDD scheme. Design and Software Implementation (C++) of the basic algorithms, logical channels (PDCCH) and initial scanning procedure. Providing unit tests and verification using Matlab LTE toolbox.- Research in area of pilot-based Channel Estimation techniques use in OFDMA receivers. Implementation of the reference models based on MMSE approach. Comparative analysis of two realizations: provided performance, implementation complexity and etc. Algorithms integration into the PHY Layer environment.- Contribution into conformance testing and L1C + PHY integration and verification. Responsible for PDCCH chain, ratematcher, DMRS signal generation and Channel Estimation.Video/Image processing algorithms development (2010-2012)- Lead the Stereo processing project. Defining the scope of work, scheduling and tracking the implementation process of a small team of junior engineers. Development and software implementation (C++) of Depth Map Estimation and Virtual View Synthesis algorithms. Performance evaluation and comparison with competitors. Development of the final application, demo preparation and project presentation at the external events.- Lead Multi-camera video tracking project. Development of visual tracking algorithm under multiple uncalibrated cameras and occlusions. Implementation (C++, OpenCV) of reference model based on Markov Chain Monte Carlo particle filter and online Support Vector Machine.

J83a. demodulator implementation on dedicated programmable accelerator (2009)Define and document algorithm mapping. Contributor to HW microarchitecture design. Profiling and comparison of results with competitors.802.16e (WiMax) standard (OFDMA PHY layer) implementation on dedicated programmable accelerator (2006-2009)- Investigation of the provided algorithms (preamble identification, frequency offset estimation, channel estimation demodulation etc.) and checking of their consistency against the standard’s specification. Software Implementation (accelerator specific high level language and assembler intrinsic) of the algorithms, their unit testing and verification. Contribution to the integral tests design and tests automation process. Development of the corresponding documentation.- Input verification of the application development tools compiler and simulators: bugs detection, specifying inefficiencies parts, requirements definition etc.- Design and Implementation of the system (SoC based on heterogeneous MESH system) profiler. Identification of the HW/SW inefficient parts. SW optimization and providing feedback to HW team.