Varun N. Email and Phone Number
Electrical Engineer with experience in Hardware Software Co-design for Mixed Signal Embedded Systems.FPGA/ASIC DESIGN- Logic design (RTL Digital Design) using Verilog, SystemVerilog, VHDL- High Level Synthesis (HLS) in C, C++, SystemC- Experience with industry standard interfaces such as PCIe, AXI, DDR, DMA- GUI or HDL based Integration of IP blocks in Block designs using standard AXI interface- Creating TCL Design constraints (XDC) to specify pin allocation, IO standards/delays, clocks, false paths- Functional Verification (driver, sequencer, monitor, scoreboard, constraint random) using UVM, CocoTB- In-circuit debugging using ILA Chipscope (TCL constraints or HDL entry) and Platform cable (JTAG) - Script driven ASIC CAD tool-flow involving specification of Target Device/Cell Library, Analysis, Environment, Constraints, Synthesis, Simulation, Reporting (timing, area, power, netlist, waveforms)- Design tools: Xilinx Vivado, Intel Quartus, Synopsys Design Compiler (DC)- Simulation tools: Mentor Graphics Questasim, Cadence Incisive- FPGA Architectures: Xilinx (Spartan, Zynq SoC, UltraScale), Intel/Altera (Cyclone III, IV SoC)PRINTED CIRCUIT BOARD DESIGN (PCB)- Schematic Capture of Analog Mixed Signal Circuits with ERC (Electrical Rule Checks)- Printed Circuit Board (PCB) Layout with DRC (Design Rule Checks)- Experience with PCB design involving components such as Mixed Signal SoC, PMIC, DAC, ADC, TDC, OpAmp, Sensors, Passive devices, Antenna, Impedance Matching Circuits (Smith charts)- Tools: KiCAD, OrCADPRACTICAL LAB SKILLS- Hands on experience using test equipment: Oscilloscope, Logic analyzer, Multimeter, Signal generator, Vector Network Analyzer (RF)- Prototyping using evaluation boards, breadboards, jumper wires, soldering.- Ability to read data sheets, user guides, schematics, PCB layout, BOM, research papersLOW-LEVEL SYSTEM SOFTWARE- Embedded Software Development (Middleware) in C++ - Firmware Development (Baremetal) in C - Algorithm Acceleration using C++, CUDA, Intel VTune for Heterogeneous Architectures (Intel Multicore CPU, NVIDIA GPU)- Baseband Signal Processing (L1) in C for 4G/LTE Base Stations (eNodeB)- Python Programming, Make files, GIT, Linux command line- Multi-threading, Event-driven & Finite State Machine design, Ultra Low power optimizations- Peripherals: SPI, I2C, UART, DMA, GPIO, Timers, Interrupts, Bluetooth Low Energy (BLE), Clock control- Mixed-Signal SoC Microcontroller(ARM): Analog Devices (ADUCM350EBZ), Nordic (NRF52832, NRF51822), Texas Instruments (MSP430)
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Fpga Design EngineerKla Jul 2021 - Present- Logic/RTL Design using Verilog, SystemVerilog- IP based block design using Xilinx Vivado.- Create design constraints for pin mapping and static timing analysis.- Testbench development and Simulation for Verification using SystemVerilog and Questasim- Model DSP algorithms in floating-point and fixed-point format using Python. - Convert Floating-point DSP designs to Fixed-point DSP designs.- Create suitable micro-architecture for fixed-point design and implement as RTL/Logic design using SystemVerilog.- Ability to trade-offs between suitable style of micro-architecture design such as iterative decomposition, time-sharing, pipelined and replication to meet latency, throughput, timing and area requirements.- RTL design, implementation, verification, timing closure and bench testing of custom controllers for Calibration, System Protection (voltage/current/temperature), XY Scanner(Fixed-point DSP), Gain Predictor (Fixed-Point DSP), DAC AD5764R Interfacing- Gained experience with Xilinx IP's and primitives (library cells) such as BRAM, IOBUF, BUFG, AXI4 Lite/Full, FIFO, MMCM, System Monitor, FIR filter, DSP, Picoblaze Soft Microprocessor (I2C Controller) and High speed serial (PCI express, Aurora 8b/10b).- Experience with both GUI and TCL based Xilinx Vivado tool flow for running synthesis, simulation, implementation (placement and routing) and bitstream generation- Writing test scripts in Python to test and validate RTL implementations on the system boards with target FPGA.- Hands-on lab experience with in-circuit debugging of FPGA logic design using ILA(Chipscope) and making measurements on boards using Function Generator, Logic Analyzer, Oscilloscope, etc.- Ability to navigate through PCB Schematics/Layout, Component Datasheets, User Guides etc. with ease- Target FPGA devices: Xilinx Zynq MPSoC, Kintex, UltraScale -
Research EngineerHonda Research Institute Usa, Inc. Jan 2021 - May 2021- Front-end and Back-end design, development and prototyping of a Wearable Sensor Electronics platform- Bare-metal Firmware Development in C- Schematic Capture and PCB layout -
Fpga Design And Verification EngineerDolby Laboratories Sep 2020 - Dec 2020Functional Verification of a Video IP using Python, CocoTB, SystemVerilog, UVM, Siemens QuestaSim simulator -
Wireless Radio EngineerMavenir May 2020 - Aug 2020Texas, United StatesDSP algorithm development in C for L1 PHY layer in LTE/4G stack -
Firmware EngineerDepartment Of Bioengineering - Ut Dallas May 2019 - Oct 2019Richardson, Texas, United StatesBaremetal firmware development in C for a Wearable Bioelectronics Platform -
Software Engineer - High Performance ComputingLexmark Oct 2013 - Jun 2016IndiaPerformance acceleration of graph, tree, 3D geometry and physics algorithms on Heterogenous Compute Nodes composed of Intel NUMA Multicore CPU's and Multiple NVIDIA GPUs -
Hardware Software Design EngineerNanotronic Oct 2012 - Dec 2012RTL Development using VHDL for Intel (Altera) FPGA'sBaremetal Firmware development in C for BLDC Motor Control -
Embedded Software DeveloperPatton Electronics Co. Sep 2011 - Apr 2012Bern, Berne, SwitzerlandEmbedded Software development in C++ -
Hardware Design Engineer - FpgaPruftechnik Group Feb 2011 - Jul 2011Munich, Bavaria, GermanyRTL design of DSP IIR Filter IP core using VHDL for Intel (Altera) Cyclone III, IV FPGA SoC
Varun N. Education Details
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Embedded Systems Design
Frequently Asked Questions about Varun N.
What company does Varun N. work for?
Varun N. works for Kla
What is Varun N.'s role at the current company?
Varun N.'s current role is FPGA Design | Embedded Systems | GPU | Hardware Software Co-design.
What schools did Varun N. attend?
Varun N. attended Eth Zürich | Usi Switzerland | Polimi Italy.
Who are Varun N.'s colleagues?
Varun N.'s colleagues are Rudy Resch, Karthik Sankaran, Xuan Xu, Itay Bretner, Hanbin Wang, Akhil S, Lemon Lin.
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