● Deevena Email & Phone Number

As a Physical Verification Engineer, I have been part of multiple projects with clients INTEL and TSMC thathave relied on my ability to work with other engineers, as well as communicate with them effectively. I haveworked on multiple blocks for signoff LV clean-up and had strong experience in Intel 7nm and TSMC N6/N3LV flows and worked on LV flows for Implementing Functional ECOs and Timing Closure ECOs (Setup &Hold Timing Violation fixing, Net Improvement, Net degradation, Cell Swaps, upsizing/downsizing cells,RV and Calibre Fix's) using Synopsys IC Compiler & IC Validator. I have also had the opportunity to honemy problem-solving skills by working on multiple issue and finding the most efficient path forward. With thehelp of my strong communication abilities, I have been able to collaborate with colleagues and technical leadsto come up with innovative solutions.