孙仪彬 Email & Phone Number

中国 上海市

1. lead a design and verification team to support processor based embedded solutions2. SOC verification for Lattice solution stacks, either C-based or UVM based stimulus3. solution specific IP design and/or optimization4. debug and optimization for Lattice FPGA based solution implementation, including timing, area, performance, etc

中国 上海

1. RISC V based SOC Integration VerificationEvaluate, define and finish whole RISC V based SOC Integration Verification:(1) Generate DUT: use software to configure and connect available RISC V core and other IPs to generate SOC HDL, compile C code which use defined drivers according to different IPs and generate binary file as stimulus to DUT;(2) finalize test goal, test plan and methodology: a) to ensure the connection and configuration of the generated SOC, develop a new UVM based simulation platform and necessary AHBLITE & APB UVC (universal verification component) to achieve pass through check for ALL valid transactions. b) to ensure driver and IP configuration, develop UART/I2C/SPI/DDR UVCs (mainly monitor, interface assertions and some necessary features for driver) (3) script for automated testbench generation: read and extract information from IPXACT based xml files for SOC and all IPs, generate register models & behavior models (for self checking purpose) for supported peripherals, generate whole testbench based on highly configurable pre-developed testbench template (almost all settings are done in config files).This project is still under development phase for at least 1 year and more features are planned to be added.

漕河泾

2. System Qualification Platform (SQP)Define, Lead and participate the development of whole SQP project: To achieve efficient higher level verification of full chip and software solution on real silicon/board, a cross team project (4 members, 2 local engineers, 2 American engineers) has been setup. The project contains: (1) a java based software(on PC) which manages the global settings, FPGA projects, daisy chain downloading and stimulus generation (SPI based packet based on FTDI cable); (2) FPGA boards and corresponding HDL designs; (3) each design is composed of Logic Platform (communicate with upper computer using SPI based packet and lower components using wishbone), simulation platform (both non-UVM/UVM versions) and components (function blocks);Beside project management and tech support, I'm also the owner of two HDL designs, several components, Logic Platform and switching simulation platform to UVM version.I published paper as first author and did presentation at CSTIC China 2017 for this project.

中国 上海

3. Software validation and silicon supportOwned the testing for timing analysis engine (engine behavior, features), timing constraints, PAR engine and QoR. Participated synthesis tool validation.In charge of silicon support : timing arc/cell model, simulation and many other device related testing for all available HW blocks(memory, dsp, etc):(1) define and optimize the testing methodology(2) manage the team as a project and team leader with ~7 members, evaluate the status and coverage, tech support for critical issues.

中国 上海

In charge of DCS (Distributed Control System) hardware update and FPGA/CPLD programmingParticipate SIMAX DCS project, enhance the schematic and PCB; create FPGA project to communicate with ARM by encoding / decoding internal system bus.

工学硕士, 控制工程

学士, 自动化